From: Ray Jui <ray.jui@broadcom.com>
To: Chris Brand <chris.brand@broadcom.com>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>,
Marc Zyngier <marc.zyngier@arm.com>,
linux-kernel@vger.kernel.org,
BCM Kernel Feedback <bcm-kernel-feedback-list@broadcom.com>,
linux-arm-kernel@lists.infradead.org,
Alex Barba <alex.barba@broadcom.com>
Subject: Re: [PATCH 1/2] dt-bindings: arm,gic: Indtroduce optional property 'arm,msi-offset-spi' for gicv2m
Date: Wed, 4 May 2016 09:11:58 -0700 [thread overview]
Message-ID: <3997ed69-760a-9bc1-a451-d07323a6e163@broadcom.com> (raw)
In-Reply-To: <CAMsMSK_jwd6OMMJ8DfAckVJgav9U6p-oz9YcinUinaqj2xdwAA@mail.gmail.com>
On 5/4/2016 8:57 AM, Chris Brand wrote:
> You have a typo in the subject line - "Indtroduce".
Thanks, but now this patch will be gone based on review comments from
Marc on PATCH 2/2.
>
> Chris
>
> On Tue, May 3, 2016 at 4:47 PM, Ray Jui <ray.jui@broadcom.com> wrote:
>> Update the GICv2m binding document by adding an optional property
>> 'arm,msi-offset-spi'.
>>
>> Some implementations of gicv2m have an erratum where the MSI data is
>> the SPI number subtracted by an offset. This is required for the
>> correct MSI interrupt to be triggered.
>>
>> Signed-off-by: Ray Jui <ray.jui@broadcom.com>
>> ---
>> Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt | 6 ++++++
>> 1 file changed, 6 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt
>> index 793c20f..550960f 100644
>> --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt
>> +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt
>> @@ -140,6 +140,12 @@ Optional properties:
>> value, this property should contain the number of
>> SPIs assigned to the frame, overriding the HW value.
>>
>> +- arm,msi-offset-spi: Some implementations of gicv2m have an erratum where
>> + the MSI data is the SPI number subtracted by an offset.
>> + This is required for the correct MSI interrupt to be
>> + triggered. This property should contain the required
>> + offset.
>> +
>> Example:
>>
>> interrupt-controller@e1101000 {
>> --
>> 2.1.4
>>
next prev parent reply other threads:[~2016-05-04 16:12 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-05-03 23:47 [PATCH 0/2] Add DT based gicv2m spi offset support Ray Jui
2016-05-03 23:47 ` [PATCH 1/2] dt-bindings: arm,gic: Indtroduce optional property 'arm,msi-offset-spi' for gicv2m Ray Jui
2016-05-04 15:57 ` Chris Brand
2016-05-04 16:11 ` Ray Jui [this message]
2016-05-03 23:47 ` [PATCH 2/2] irqchip/gic-v2m: Add workaround for Broadcom NS2 GICv2m erratum Ray Jui
2016-05-04 7:49 ` Marc Zyngier
2016-05-04 16:20 ` Ray Jui
2016-05-04 17:25 ` Marc Zyngier
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