From: Claudiu Beznea <claudiu.beznea@tuxon.dev>
To: Varshini Rajendran <varshini.rajendran@microchip.com>,
mturquette@baylibre.com, sboyd@kernel.org,
nicolas.ferre@microchip.com, alexandre.belloni@bootlin.com,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Cc: Patrice Vilchez <Patrice.Vilchez@microchip.com>
Subject: Re: [PATCH v2] clk: at91: sam9x7: update pll clk ranges
Date: Fri, 18 Jul 2025 09:45:02 +0300 [thread overview]
Message-ID: <39b57899-4e8d-445f-a3b5-3b7f9ba3c3cb@tuxon.dev> (raw)
In-Reply-To: <20250714093512.29944-1-varshini.rajendran@microchip.com>
On 14.07.2025 12:35, Varshini Rajendran wrote:
> Update the min, max ranges of the PLL clocks according to the latest
> datasheet to be coherent in the driver. This patch solves the issues in
> configuring the clocks related to peripherals with the desired frequency
> within the range.
>
> Fixes: 33013b43e271 ("clk: at91: sam9x7: add sam9x7 pmc driver")
> Suggested-by: Patrice Vilchez <Patrice.Vilchez@microchip.com>
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Applied to clk-microchip, thanks!
prev parent reply other threads:[~2025-07-18 6:45 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-14 9:35 Varshini Rajendran
2025-07-18 6:45 ` Claudiu Beznea [this message]
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