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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-af635adb093sm590411066b.124.2025.07.29.06.32.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 29 Jul 2025 06:32:35 -0700 (PDT) Message-ID: <39be83ee-9aa3-4c87-b76b-b6dcaf50a239@oss.qualcomm.com> Date: Tue, 29 Jul 2025 15:32:30 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v7 2/3] arm64: dts: qcom: sa8775p: remove aux clock from pcie phy To: Ziyue Zhang , andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, jingoohan1@gmail.com, mani@kernel.org, lpieralisi@kernel.org, kwilczynski@kernel.org, bhelgaas@google.com, johan+linaro@kernel.org, vkoul@kernel.org, kishon@kernel.org, neil.armstrong@linaro.org, abel.vesa@linaro.org, kw@linux.com Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, qiang.yu@oss.qualcomm.com, quic_krichai@quicinc.com, quic_vbadigan@quicinc.com References: <20250725102231.3608298-1-ziyue.zhang@oss.qualcomm.com> <20250725102231.3608298-3-ziyue.zhang@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20250725102231.3608298-3-ziyue.zhang@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI5MDEwNCBTYWx0ZWRfX3uGR8injBv77 UMu5Z/BH1j4pPCyCBdd8jbC/fc3pr2IzuRJCBmcoHRWo2cH9mv6pX74RNna6kZDtcZindzOEpse Zhorz/xA1/Cm3JdKfnghIqMHueBJhCH39Uc+U6tgAOzAEkwkUwsX5biikxAZ7iqLVYEsfcQYfx7 xL6pObmgUL9N5z+JJXvnBNS2oQsjmZm2oHBGDgoIYZ8/rqstTtG9TG6fyt11YJOUPtFfIc7ub6u 9qHHiGE13wPTyD1oNytuUAlEQ/hNuZ81a9/YyYG0MH3V3x2bh+q0bpTd1fmd1pDkuJehwLoP8Tc mogDohVbMc21uQ8+/xMJK7w/2Yw5OCccQDizLjqqLPDUBj8JhJxhid3R1UZwVMgAawUlTbsmynu k6ThBQqzZuSy6UPSNtPaDveYDvoXlNyLosLEaIsE1M+UEe7pxkDUMY3MUhkoPtOvDrHR3649 X-Authority-Analysis: v=2.4 cv=Hth2G1TS c=1 sm=1 tr=0 ts=6888cd76 cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=8Yr4R-HfXjpLVZqX0moA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 X-Proofpoint-GUID: 5O05eBIXy9tfpu3HlqA3f8cCcmQIofIp X-Proofpoint-ORIG-GUID: 5O05eBIXy9tfpu3HlqA3f8cCcmQIofIp X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-29_03,2025-07-28_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 mlxscore=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 adultscore=0 malwarescore=0 mlxlogscore=999 clxscore=1015 spamscore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507290104 On 7/25/25 12:22 PM, Ziyue Zhang wrote: > The gcc_aux_clk is used by the PCIe Root Complex (RC) and is not required > by the PHY. The correct clock for the PHY is gcc_phy_aux_clk, which this > patch uses to replace the incorrect reference. > > The distinction between AUX_CLK and PHY_AUX_CLK is important: AUX_CLK is > typically used by the controller, while PHY_AUX_CLK is required by certain > PHYs—particularly Gen4 QMP PHYs—for internal operations such as clock > gating and power management. Some non-Gen4 Qualcomm PHYs also use > PHY_AUX_CLK, but they do not require AUX_CLK. > > This change ensures proper clock configuration and avoids unnecessary > dependencies. > > Signed-off-by: Ziyue Zhang > --- Fixes: 489f14be0e0a ("arm64: dts: qcom: sa8775p: Add pcie0 and pcie1 nodes") Konrad