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[93.144.65.244]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-490b63d8205sm33175305e9.11.2026.06.03.01.25.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jun 2026 01:25:10 -0700 (PDT) From: Stefano Radaelli X-Google-Original-From: Stefano Radaelli To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: pierluigi.p@variscite.com, Stefano Radaelli , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Subject: [PATCH v3 4/5] arm64: dts: imx93-var-som-symphony: enable TPM3 PWM Date: Wed, 3 Jun 2026 10:25:03 +0200 Message-ID: <39bfb7ce8a40d041f2f23344eadeb641a1cf9275.1780474803.git.stefano.r@variscite.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Stefano Radaelli Enable TPM3 on the Symphony carrier board and add the pinctrl states for the PWM output and sleep configuration. Signed-off-by: Stefano Radaelli --- v2->v3: - v1->v2: - .../dts/freescale/imx93-var-som-symphony.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts index c835394468ef..56f8744c861a 100644 --- a/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts @@ -320,6 +320,13 @@ &lpuart7 { status = "okay"; }; +&tpm3 { + pinctrl-0 = <&pinctrl_tpm3>; + pinctrl-1 = <&pinctrl_tpm3_sleep>; + pinctrl-names = "default", "sleep"; + status = "okay"; +}; + &usbotg1 { dr_mode = "otg"; hnp-disable; @@ -442,6 +449,18 @@ MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x31e >; }; + pinctrl_tpm3: tpm3grp { + fsl,pins = < + MX93_PAD_GPIO_IO24__TPM3_CH3 0x51e + >; + }; + + pinctrl_tpm3_sleep: tpm3sleepgrp { + fsl,pins = < + MX93_PAD_GPIO_IO24__GPIO2_IO24 0x51e + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX93_PAD_UART1_RXD__LPUART1_RX 0x31e -- 2.47.3