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Received: from PH7PR12MB9174.namprd12.prod.outlook.com (2603:10b6:510:2ed::9) by CY3PR12MB9578.namprd12.prod.outlook.com (2603:10b6:930:109::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.592.10; Thu, 5 Nov 2026 17:46:41 +0000 Received: from PH7PR12MB9174.namprd12.prod.outlook.com ([fe80::eaaa:b430:ba9:5dc]) by PH7PR12MB9174.namprd12.prod.outlook.com ([fe80::eaaa:b430:ba9:5dc%7]) with mapi id 15.21.0592.007; Thu, 5 Nov 2026 17:46:40 +0000 Message-ID: <39c2d670-4876-41be-ac90-af3db8faca8b@amd.com> Date: Thu, 5 Nov 2026 11:46:36 -0600 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] pinctrl: amd: Clear interrupt enable bit on spurious GPIO IRQ Content-Language: en-US To: Munique Feitoza , Linus Walleij Cc: "Mario Limonciello (AMD)" , Basavaraj Natikar , Shyam Sundar S K , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, sashiko-bot@kernel.org References: <20261030195025.5153-1-muniquefeitoz4@gmail.com> <20261030200827.24648-1-muniquefeitoz4@gmail.com> From: Mario Limonciello In-Reply-To: Content-Type: text/plain; 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Unlike amd_gpio_irq_disable(), leaving >>> INTERRUPT_ENABLE_OFF enabled allows the pin interrupt status bit to >>> keep asserting in WAKE_INT_STATUS_REG0/1. >>> >>> Clear both INTERRUPT_MASK_OFF and INTERRUPT_ENABLE_OFF when disabling >>> a spurious GPIO IRQ on both the main and RGPIO banks. >>> >>> Signed-off-by: Munique Feitoza I'd like to understand more about this situation that lead you to this patch before we decide which way to go on the patch. Was this just analyzing the code and looking for a code flow problem? Or do you have a real problem on a real system and came up with this to fix it?