From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7627B43744D for ; Tue, 21 Jul 2026 08:08:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784621330; cv=none; b=c3/XiFMIKAG6ih57WRd8GTFY+YLp1lnFssJPg07TRnYEr3p01W74QS95kUPRWYWe+Q2HvtH5djXurBHG00iOSV22Kgu+I8x9GQ9Nr99IPV+XZVsmwIf999lHHkStbqR/k5puqCpviTmb3V7BhhOa5oEm0FCSBdP7k3S1gvAEWj4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784621330; c=relaxed/simple; bh=HZYvMxti+/VF6/4xV8YFEXtDdF4wi4FunN44FdB1v/M=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=gtpnLbP2ljwhWi7w5wEsRhNhcMjyefuckfwGAVtJkuBQ1eX3AJu6RyCy3MXTuJbxPAL746Sh2ZlAE6pp5Gg09tZtCD4M+KZ5Kcabc12dr5797wR38CW8tcKPCj7LauB13Ad2gpeuTmfOz4wjY8ny4qeaKVxuiS36aolw8lmXZW8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=WcqDq9PT; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="WcqDq9PT" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 547A51F000E9; Tue, 21 Jul 2026 08:08:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1784621329; bh=jWALWuCiJTSNWsIDvJiatv/9uq8jU28MTEy/bFj2a1A=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=WcqDq9PTZv6a4TziDr2AvdoFatw+EHOpL0ESx41AfWSHX2rBvH2j0GBoSZnLw95Kh p41vnGufI/ptD7gaf1KlsT/ibUa9S/1oGMjU39vepFupD8Lo1WfLZdQqi8xiEfSIGB qVIRxCy/WoR2T9qUf0SWqJ5J5YgFI5Dn7txOAoSLPw/HXjO1s34enH94iWkjmSKbOt 4zMjqncRXzBz2D43+70uhlRSA+SX0vtpvZ4CNbVEMudfYRcfzBTQTgDorpx/9PJXft 6ZD+1DsUMxF7eXkzaWTOMWlcu5daNZ27n7trFSk+byXpdujMZ0yROk+WOiWpvlHPVd 27H9gZh3GOf5w== From: "Naveen N Rao (AMD)" To: Borislav Petkov , Dave Hansen Cc: , , Nikunj A Dadhania , Manali Shukla , Bharata B Rao , "H. Peter Anvin" , Thomas Gleixner Subject: [PATCH v3 2/3] x86/apic: Introduce a variable to track the number of EILVT registers Date: Tue, 21 Jul 2026 13:33:36 +0530 Message-ID: <39d39c3b91d174f4090fb954c6690edae9ed8295.1784619898.git.naveen@kernel.org> X-Mailer: git-send-email 2.54.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Future AMD processors will be increasing the number of EILVT registers. Rather than hardcoding the maximum EILVT register count and using that everywhere, introduce a variable to track the EILVT register count. The number of EILVT registers (the actual count) is exposed through the extended APIC Feature Register (APIC_EFEAT) bits 23:16. Use this to initialize the count and fall back to the current default (APIC_EILVT_NR_AMD_10H) if the count is not available. Signed-off-by: Naveen N Rao (AMD) Tested-by: Manali Shukla --- arch/x86/include/asm/apic.h | 2 ++ arch/x86/include/asm/apicdef.h | 1 + arch/x86/kernel/apic/apic.c | 11 +++++++++++ 3 files changed, 14 insertions(+) diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h index 9cd493d467d4..8b03c7a14706 100644 --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -74,6 +74,8 @@ enum apic_intr_mode_id { APIC_SYMMETRIC_IO_NO_ROUTING }; +extern unsigned int apic_eilvt_count; + /* * With 82489DX we can't rely on apic feature bit * retrieved via cpuid but still have to deal with diff --git a/arch/x86/include/asm/apicdef.h b/arch/x86/include/asm/apicdef.h index bc125c4429dc..ba7657e75ad1 100644 --- a/arch/x86/include/asm/apicdef.h +++ b/arch/x86/include/asm/apicdef.h @@ -134,6 +134,7 @@ #define APIC_TDR_DIV_64 0x9 #define APIC_TDR_DIV_128 0xA #define APIC_EFEAT 0x400 +#define APIC_EFEAT_XLC(x) (((x) >> 16) & 0xff) #define APIC_ECTRL 0x410 #define APIC_SEOI 0x420 #define APIC_IER 0x480 diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index 90025451ace2..83895ce954ef 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -342,6 +342,7 @@ static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) */ static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; +unsigned int apic_eilvt_count __ro_after_init; static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) { @@ -410,6 +411,15 @@ int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) } EXPORT_SYMBOL_GPL(setup_APIC_eilvt); +static __init void init_eilvt(void) +{ + if (cpu_feature_enabled(X86_FEATURE_EXTAPIC)) + apic_eilvt_count = APIC_EFEAT_XLC(apic_read(APIC_EFEAT)); + + if (!apic_eilvt_count && boot_cpu_data.x86_vendor == X86_VENDOR_AMD) + apic_eilvt_count = APIC_EILVT_NR_AMD_10H; +} + /* * Program the next event, relative to now */ @@ -2345,6 +2355,7 @@ static void __init apic_bsp_setup(bool upmode) if (upmode) apic_bsp_up_setup(); setup_local_APIC(); + init_eilvt(); enable_IO_APIC(); end_local_APIC_setup(); -- 2.54.0