diff -U3 -rN scsi.save/aic7xxx/aic7xxx.seq scsi/aic7xxx/aic7xxx.seq --- scsi.save/aic7xxx/aic7xxx.seq Wed Feb 7 15:07:28 2001 +++ scsi/aic7xxx/aic7xxx.seq Thu Feb 8 01:52:38 2001 @@ -291,11 +291,7 @@ mov A, LASTPHASE; - if ((p->features & AHC_ULTRA2) != 0) { - test A, ~P_DATAIN jz u2_p_data; - } else { - test A, ~P_DATAIN jz p_data; - } + test A, ~P_DATAIN jz p_data; cmp A,P_COMMAND je p_command; cmp A,P_MESGOUT je p_mesgout; cmp A,P_STATUS je p_status; @@ -336,73 +332,130 @@ /* clear target specific flags */ clr SEQ_FLAGS ret; - if ((p->features & AHC_ULTRA2) != 0) { - - -u2_data_phase_reinit: +data_phase_reinit: /* * If we re-enter the data phase after going through another phase, the * STCNT may have been cleared, so restore it from the residual field. * On Ultra2, we have to put it into the HCNT field because we have to * drop the data down into the shadow layer via the preload ability. */ + if ((p->features & AHC_ULTRA2) != 0) { bmov HADDR, SHADDR, 4; bmov HCNT, SCB_RESID_DCNT, 3; - jmp u2_data_phase_loop; -u2_p_data: + } + if ((p->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { + bmov STCNT, SCB_RESID_DCNT, 3; + } + if ((p->features & AHC_CMD_CHAN) == 0) { + mvi DINDEX, STCNT; + mvi SCB_RESID_DCNT call bcopy_3; + } + jmp data_phase_loop; +p_data: + if ((p->features & AHC_ULTRA2) != 0) { mvi DMAPARAMS, PRELOADEN|SCSIEN|HDMAEN; - test LASTPHASE, IOI jnz . + 2; - or DMAPARAMS, DIRECTION; - call assert; /* - * Ensure entering a data - * phase is okay - seen identify, etc. - */ + } else { + mvi DMAPARAMS, WIDEODD|SCSIEN|SDMAEN|HDMAEN|FIFORESET; + } + test LASTPHASE, IOI jnz . + 2; + or DMAPARAMS, DIRECTION; + call assert; /* + * Ensure entering a data + * phase is okay - seen identify, etc. + */ + if ((p->features & AHC_CMD_CHAN) != 0) { mvi CCSGADDR, CCSGADDR_MAX; - test SEQ_FLAGS, DPHASE jnz u2_data_phase_reinit; - or SEQ_FLAGS, DPHASE; /* we've seen a data phase */ - /* - * Initialize the DMA address and counter from the SCB. - * Also set SG_COUNT and SG_NEXT in memory since we cannot - * modify the values in the SCB itself until we see a - * save data pointers message. - */ + } + + test SEQ_FLAGS, DPHASE jnz data_phase_reinit; + or SEQ_FLAGS, DPHASE; /* we've seen a data phase */ + /* + * Initialize the DMA address and counter from the SCB. + * Also set SG_COUNT and SG_NEXT in memory since we cannot + * modify the values in the SCB itself until we see a + * save data pointers message. + */ + if ((p->features & AHC_CMD_CHAN) != 0) { bmov HADDR, SCB_DATAPTR, 7; bmov SG_COUNT, SCB_SGCOUNT, 5; -u2_data_phase_loop: - /* Guard against overruns */ - test SG_COUNT, 0xff jnz u2_data_phase_inbounds; + if ((p->features & AHC_ULTRA2) == 0) { + bmov STCNT, HCNT, 3; + } + } else { + mvi DINDEX, HADDR; + mvi SCB_DATAPTR call bcopy_7; + call set_stcnt_from_hcnt; + mvi DINDEX, SG_COUNT; + mvi SCB_SGCOUNT call bcopy_5; + } +data_phase_loop: + /* Guard against overruns */ + test SG_COUNT, 0xff jnz data_phase_inbounds; /* * Turn on 'Bit Bucket' mode, set the transfer count to * 16meg and let the target run until it changes phase. * When the transfer completes, notify the host that we * had an overrun. */ - or SXFRCTL1,BITBUCKET; - and DMAPARAMS, DIRECTION; + or SXFRCTL1,BITBUCKET; + and DMAPARAMS, ~(HDMAEN|SDMAEN); + if ((p->features & AHC_ULTRA2) != 0) { bmov HCNT, ALLONES, 3; -u2_data_phase_inbounds: + } + if ((p->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { + bmov STCNT, ALLONES, 3; + } + if ((p->features & AHC_CMD_CHAN) == 0) { + mvi STCNT[0], 0xFF; + mvi STCNT[1], 0xFF; + mvi STCNT[2], 0xFF; + } + +data_phase_inbounds: /* If we are the last SG block, tell the hardware. */ + if ((p->features & AHC_ULTRA2) != 0) { shl A, 2, SG_COUNT; - cmp SG_COUNT,0x01 jne u2_data_phase_lastseg; + cmp SG_COUNT,0x01 jne data_phase_wideodd; or A, LAST_SEG; -u2_data_phase_lastseg: + } else { + cmp SG_COUNT,0x01 jne data_phase_wideodd; + and DMAPARAMS, ~WIDEODD; + } +data_phase_wideodd: + if ((p->features & AHC_ULTRA2) != 0) { mov SG_CACHEPTR, A; mov DFCNTRL, DMAPARAMS; /* start the operation */ - test SXFRCTL1, BITBUCKET jnz u2_data_phase_overrun; + test SXFRCTL1, BITBUCKET jnz data_phase_overrun; u2_preload_wait: test SSTAT1, PHASEMIS jnz u2_phasemis; test DFSTATUS, PRELOAD_AVAIL jz u2_preload_wait; + } else { + mov DMAPARAMS call dma; +data_phase_dma_done: +/* Go tell the host about any overruns */ + test SXFRCTL1,BITBUCKET jnz data_phase_overrun; + +/* Exit if we had an underrun. dma clears SINDEX in this case. */ + test SINDEX,0xff jz data_phase_finish; + } /* * Advance the scatter-gather pointers */ -u2_sg_advance: +sg_advance: + if ((p->features & AHC_ULTRA2) != 0) { cmp SG_COUNT, 0x01 je u2_data_phase_finish; + } else { + dec SG_COUNT; + test SG_COUNT, 0xff jz data_phase_finish; + } + + if ((p->features & AHC_CMD_CHAN) != 0) { /* * Do we have any prefetch left??? */ - cmp CCSGADDR, CCSGADDR_MAX jne u2_prefetch_avail; + cmp CCSGADDR, CCSGADDR_MAX jne prefetch_avail; /* * Fetch MIN(CCSGADDR_MAX, (SG_COUNT * 8)) bytes. @@ -418,18 +471,48 @@ and CCSGCTL, ~CCSGEN; test CCSGCTL, CCSGEN jnz .; mvi CCSGCTL, CCSGRESET; -u2_prefetch_avail: - /* Test for a phasemis before we drop the stuff into the - * host regs. We might have actually missed the phasemis - * while doing the dma of the sg segs. - */ - test SSTAT1, PHASEMIS jnz u2_phasemis; - dec SG_COUNT; /* one less segment to go */ - bmov HADDR, CCSGRAM, 8; /* drop the address in place */ - clr A; /* Advance the SG pointer by */ - add SG_NEXT[0],SG_SIZEOF; /* adding SG_SIZEOF to addr0 */ - adc SG_NEXT[1],A; /* and adding any carry to */ - jmp u2_data_phase_loop; /* addr1 */ +prefetch_avail: + bmov HADDR, CCSGRAM, 8; + if ((p->features & AHC_ULTRA2) == 0) { + bmov STCNT, HCNT, 3; + } else { + dec SG_COUNT; + } + } else { + mvi DINDEX, HADDR; + mvi SG_NEXT call bcopy_4; + + mvi HCNT[0],SG_SIZEOF; + clr HCNT[1]; + clr HCNT[2]; + + or DFCNTRL, HDMAEN|DIRECTION|FIFORESET; + + call dma_finish; + +/* + * Copy data from FIFO into SCB data pointer and data count. + * This assumes that the SG segments are of the form: + * struct ahc_dma_seg { + * u_int32_t addr; four bytes, little-endian order + * u_int32_t len; four bytes, little endian order + * }; + */ + mvi DINDEX, HADDR; + call dfdat_in_7; + call set_stcnt_from_hcnt; + } +/* Advance the SG pointer */ + clr A; /* add sizeof(struct scatter) */ + add SG_NEXT[0],SG_SIZEOF; + adc SG_NEXT[1],A; + + if ((p->features & AHC_ULTRA2) != 0) { + jmp data_phase_loop; + } else { + test SSTAT1, REQINIT jz .; + test SSTAT1,PHASEMIS jz data_phase_loop; + } /* @@ -438,23 +521,24 @@ * we'll get a phasemis if we do finish, all we really need to do is wait * for a phasemis then check if we did actually complete all the segments. */ + if ((p->features & AHC_ULTRA2) != 0) { u2_data_phase_finish: test SSTAT1, PHASEMIS jnz u2_phasemis; test SG_CACHEPTR, LAST_SEG_DONE jz u2_data_phase_finish; clr SG_COUNT; test SSTAT1, REQINIT jz .; - test SSTAT1, PHASEMIS jz u2_data_phase_loop; + test SSTAT1, PHASEMIS jz data_phase_loop; u2_phasemis: call ultra2_dmafinish; - test SG_CACHEPTR, LAST_SEG_DONE jnz u2_phasemis_end; + test SG_CACHEPTR, LAST_SEG_DONE jnz data_phase_finish; test SSTAT2, SHVALID jnz u2_fixup_residual; mvi INTSTAT, SEQ_SG_FIXUP; - jmp u2_phasemis_end; + jmp data_phase_finish; u2_fixup_residual: shr ARG_1, 2, SG_CACHEPTR; u2_phasemis_loop: and A, 0x3f, SG_COUNT; - cmp ARG_1, A je u2_phasemis_end; + cmp ARG_1, A je data_phase_finish; /* * Subtract SG_SIZEOF from the SG_NEXT pointer and add 1 to the SG_COUNT */ @@ -463,11 +547,44 @@ adc SG_NEXT[1], 0xff; inc SG_COUNT; jmp u2_phasemis_loop; -u2_phasemis_end: - bmov SCB_RESID_DCNT, STCNT, 3; + } + +data_phase_finish: +/* + * After a DMA finishes, save the SG and STCNT residuals back into the SCB + * We use STCNT instead of HCNT, since it's a reflection of how many bytes + * were transferred on the SCSI (as opposed to the host) bus. + */ + if ((p->features & AHC_CMD_CHAN) != 0) { + bmov SCB_RESID_DCNT, STCNT, 3; mov SCB_RESID_SGCNT, SG_COUNT; - or SXFRCTL0, CLRSTCNT|CLRCHN; - jmp ITloop; + if ((p->features & AHC_ULTRA2) != 0) { + or SXFRCTL0, CLRSTCNT|CLRCHN; + } + } else { + mov SCB_RESID_DCNT[0],STCNT[0]; + mov SCB_RESID_DCNT[1],STCNT[1]; + mov SCB_RESID_DCNT[2],STCNT[2]; + mov SCB_RESID_SGCNT, SG_COUNT; + } + + jmp ITloop; + +data_phase_overrun: +/* + * Turn off BITBUCKET mode and notify the host + */ + if ((p->features & AHC_ULTRA2) != 0) { +/* + * Wait for the target to quit transferring data on the SCSI bus + */ + test SSTAT1, PHASEMIS jz .; + call ultra2_dmafinish; + } + and SXFRCTL1, ~BITBUCKET; + mvi INTSTAT,DATA_OVERRUN; + jmp ITloop; + @@ -478,6 +595,7 @@ * brought into the data phase again (or are still in it after our last * segment) that we will properly signal an overrun to the kernel. */ + if ((p->features & AHC_ULTRA2) != 0) { ultra2_dmafinish: test DFCNTRL, DIRECTION jnz ultra2_dmahalt; and DFCNTRL, ~SCSIEN; @@ -515,196 +633,6 @@ and DFCNTRL, ~(HDMAEN|SCSIEN); test DFCNTRL, (HDMAEN|SCSIEN) jnz .; ret; - -u2_data_phase_overrun: -/* - * Wait for the target to quit transferring data on the SCSI bus - */ - test SSTAT1, PHASEMIS jz .; - call ultra2_dmafinish; -/* - * Turn off BITBUCKET mode and notify the host - */ - and SXFRCTL1, ~BITBUCKET; - mvi INTSTAT,DATA_OVERRUN; - jmp ITloop; - - - - } else { /* NOT Ultra2 */ - - - -data_phase_reinit: -/* - * If we re-enter the data phase after going through another phase, the - * STCNT may have been cleared, so restore it from the residual field. - */ - if ((p->features & AHC_CMD_CHAN) != 0) { - bmov STCNT, SCB_RESID_DCNT, 3; - } else { - mvi DINDEX, STCNT; - mvi SCB_RESID_DCNT call bcopy_3; - } - jmp data_phase_loop; -p_data: - mvi DMAPARAMS, WIDEODD|SCSIEN|SDMAEN|HDMAEN|FIFORESET; - test LASTPHASE, IOI jnz . + 2; - or DMAPARAMS, DIRECTION; - call assert; /* - * Ensure entering a data - * phase is okay - seen identify, etc. - */ - if ((p->features & AHC_CMD_CHAN) != 0) { - mvi CCSGADDR, CCSGADDR_MAX; - } - test SEQ_FLAGS, DPHASE jnz data_phase_reinit; - or SEQ_FLAGS, DPHASE; /* we've seen a data phase */ - /* - * Initialize the DMA address and counter from the SCB. - * Also set SG_COUNT and SG_NEXT in memory since we cannot - * modify the values in the SCB itself until we see a - * save data pointers message. - */ - if ((p->features & AHC_CMD_CHAN) != 0) { - bmov HADDR, SCB_DATAPTR, 7; - bmov STCNT, HCNT, 3; - bmov SG_COUNT, SCB_SGCOUNT, 5; - } else { - mvi DINDEX, HADDR; - mvi SCB_DATAPTR call bcopy_7; - call set_stcnt_from_hcnt; - mvi DINDEX, SG_COUNT; - mvi SCB_SGCOUNT call bcopy_5; - } -data_phase_loop: - /* Guard against overruns */ - test SG_COUNT, 0xff jnz data_phase_inbounds; -/* - * Turn on 'Bit Bucket' mode, set the transfer count to - * 16meg and let the target run until it changes phase. - * When the transfer completes, notify the host that we - * had an overrun. - */ - or SXFRCTL1,BITBUCKET; - and DMAPARAMS, ~(HDMAEN|SDMAEN); - if ((p->features & AHC_CMD_CHAN) != 0) { - bmov STCNT, ALLONES, 3; - } else { - mvi STCNT[0], 0xFF; - mvi STCNT[1], 0xFF; - mvi STCNT[2], 0xFF; - } - -data_phase_inbounds: -/* If we are the last SG block, tell the hardware. */ - cmp SG_COUNT,0x01 jne data_phase_wideodd; - and DMAPARAMS, ~WIDEODD; -data_phase_wideodd: - mov DMAPARAMS call dma; -data_phase_dma_done: -/* Go tell the host about any overruns */ - test SXFRCTL1,BITBUCKET jnz data_phase_overrun; - -/* Exit if we had an underrun. dma clears SINDEX in this case. */ - test SINDEX,0xff jz data_phase_finish; -/* - * Advance the scatter-gather pointers if needed - */ -sg_advance: - cmp SG_COUNT, 0x01 je data_phase_finish; /* Are we done? */ - dec SG_COUNT; /* one less segment to go */ -/* - * Load a struct scatter and set up the data address and length. - * If the working value of the SG count is nonzero, then - * we need to load a new set of values. - * - * This, like all DMA's, assumes little-endian host data storage. - */ -sg_load: - if ((p->features & AHC_CMD_CHAN) != 0) { - /* - * Do we have any prefetch left??? - */ - cmp CCSGADDR, CCSGADDR_MAX jne prefetch_avail; - - /* - * Fetch MIN(CCSGADDR_MAX, (SG_COUNT * 8)) bytes. - */ - add A, -(CCSGRAM_MAXSEGS + 1), SG_COUNT; - mvi A, CCSGADDR_MAX; - jc . + 2; - shl A, 3, SG_COUNT; - mov CCHCNT, A; - bmov CCHADDR, SG_NEXT, 4; - mvi CCSGCTL, CCSGEN|CCSGRESET; - test CCSGCTL, CCSGDONE jz .; - and CCSGCTL, ~CCSGEN; - test CCSGCTL, CCSGEN jnz .; - mvi CCSGCTL, CCSGRESET; -prefetch_avail: - bmov HADDR, CCSGRAM, 8; - bmov STCNT, HCNT, 3; - } else { - mvi DINDEX, HADDR; - mvi SG_NEXT call bcopy_4; - - mvi HCNT[0],SG_SIZEOF; - clr HCNT[1]; - clr HCNT[2]; - - or DFCNTRL, HDMAEN|DIRECTION|FIFORESET; - - call dma_finish; - -/* - * Copy data from FIFO into SCB data pointer and data count. - * This assumes that the SG segments are of the form: - * struct ahc_dma_seg { - * u_int32_t addr; four bytes, little-endian order - * u_int32_t len; four bytes, little endian order - * }; - */ - mvi HADDR call dfdat_in_7; - call set_stcnt_from_hcnt; - } -/* Advance the SG pointer */ - clr A; /* add sizeof(struct scatter) */ - add SG_NEXT[0],SG_SIZEOF; - adc SG_NEXT[1],A; - - test SSTAT1, REQINIT jz .; - test SSTAT1,PHASEMIS jz data_phase_loop; - -data_phase_finish: -/* - * After a DMA finishes, save the SG and STCNT residuals back into the SCB - * We use STCNT instead of HCNT, since it's a reflection of how many bytes - * were transferred on the SCSI (as opposed to the host) bus. - */ - clr SG_COUNT; - if ((p->features & AHC_CMD_CHAN) != 0) { - bmov SCB_RESID_DCNT, STCNT, 3; - mov SCB_RESID_SGCNT, SG_COUNT; - } else { - mov SCB_RESID_DCNT[0],STCNT[0]; - mov SCB_RESID_DCNT[1],STCNT[1]; - mov SCB_RESID_DCNT[2],STCNT[2]; - mov SCB_RESID_SGCNT, SG_COUNT; - } - - jmp ITloop; - -data_phase_overrun: -/* - * Turn off BITBUCKET mode and notify the host - */ - and SXFRCTL1, ~BITBUCKET; - mvi INTSTAT,DATA_OVERRUN; - jmp ITloop; - - - } /* @@ -1437,21 +1365,25 @@ bmov CCSCBRAM, SCB_CONTROL, 32; or CCSCBCTL, CCSCBEN|CCSCBRESET; test CCSCBCTL, CCSCBDONE jz .; - } else if ((p->bugs & AHC_BUG_SCBCHAN_UPLOAD) != 0) { - mvi CCSCBCTL, CCARREN|CCSCBRESET; - cmp CCSCBCTL, ARRDONE|CCARREN jne .; - mvi CCHCNT, 32; - mvi CCSCBCTL, CCSCBEN|CCSCBRESET; - cmp CCSCBCTL, CCSCBDONE|CCSCBEN jne .; - } else { - mvi CCSCBCTL, CCARREN|CCSCBEN|CCSCBRESET; - cmp CCSCBCTL, CCSCBDONE|ARRDONE|CCARREN|CCSCBEN jne .; + } + if ((p->features & AHC_ULTRA2) != 0) { + if ((p->bugs & AHC_BUG_SCBCHAN_UPLOAD) != 0) { + mvi CCSCBCTL, CCARREN|CCSCBRESET; + cmp CCSCBCTL, ARRDONE|CCARREN jne .; + mvi CCHCNT, 32; + mvi CCSCBCTL, CCSCBEN|CCSCBRESET; + cmp CCSCBCTL, CCSCBDONE|CCSCBEN jne .; + } else { + mvi CCSCBCTL, CCARREN|CCSCBEN|CCSCBRESET; + cmp CCSCBCTL, CCSCBDONE|ARRDONE|CCARREN|CCSCBEN jne .; + } } dma_scb_finish: clr CCSCBCTL; test CCSCBCTL, CCARREN|CCSCBEN jnz .; ret; - } else { + } + if ((p->features & AHC_CMD_CHAN) == 0) { mvi DINDEX, HADDR; mvi HSCB_ADDR call set_32byte_addr; mvi HCNT[0], 32; diff -U3 -rN scsi.save/aic7xxx/aic7xxx_seq.c scsi/aic7xxx/aic7xxx_seq.c --- scsi.save/aic7xxx/aic7xxx_seq.c Wed Feb 7 15:07:28 2001 +++ scsi/aic7xxx/aic7xxx_seq.c Thu Feb 8 01:52:38 2001 @@ -7,7 +7,7 @@ 0x12, 0x6a, 0x00, 0x00, 0xff, 0x6a, 0xd6, 0x09, 0xff, 0x6a, 0xdc, 0x09, - 0x00, 0x65, 0xcc, 0x58, + 0x00, 0x65, 0xca, 0x58, 0xf7, 0x01, 0x02, 0x08, 0xff, 0x4e, 0xc8, 0x08, 0xbf, 0x60, 0xc0, 0x08, @@ -25,12 +25,12 @@ 0x00, 0x4d, 0x10, 0x70, 0x01, 0x4e, 0x9c, 0x18, 0xbf, 0x60, 0xc0, 0x08, - 0x00, 0x6a, 0xce, 0x5c, + 0x00, 0x6a, 0x86, 0x5c, 0xff, 0x4e, 0xc8, 0x18, - 0x02, 0x6a, 0xb8, 0x5b, + 0x02, 0x6a, 0x70, 0x5b, 0xff, 0x52, 0x20, 0x09, 0x0d, 0x6a, 0x6a, 0x00, - 0x00, 0x52, 0x2e, 0x5c, + 0x00, 0x52, 0xe6, 0x5b, 0x03, 0xb0, 0x52, 0x31, 0xff, 0xb0, 0x52, 0x09, 0xff, 0xb1, 0x54, 0x09, @@ -87,21 +87,20 @@ 0x08, 0x6a, 0x66, 0x58, 0x80, 0x6a, 0x68, 0x00, 0x80, 0x36, 0x6c, 0x00, - 0x00, 0x65, 0x02, 0x5c, + 0x00, 0x65, 0xba, 0x5b, 0xff, 0x3d, 0xc8, 0x08, - 0xbf, 0x64, 0xde, 0x78, - 0xbf, 0x64, 0x88, 0x79, - 0x80, 0x64, 0x10, 0x72, - 0xa0, 0x64, 0x40, 0x72, - 0xc0, 0x64, 0x38, 0x72, - 0xe0, 0x64, 0x80, 0x72, + 0xbf, 0x64, 0xe2, 0x78, + 0x80, 0x64, 0xc8, 0x71, + 0xa0, 0x64, 0xf8, 0x71, + 0xc0, 0x64, 0xf0, 0x71, + 0xe0, 0x64, 0x38, 0x72, 0x01, 0x6a, 0x22, 0x01, 0x00, 0x65, 0xaa, 0x40, 0xf7, 0x11, 0x22, 0x08, - 0x00, 0x65, 0xcc, 0x58, + 0x00, 0x65, 0xca, 0x58, 0xff, 0x06, 0xd4, 0x08, 0xf7, 0x01, 0x02, 0x08, - 0x09, 0x0c, 0xc6, 0x78, + 0x09, 0x0c, 0xc4, 0x78, 0x08, 0x0c, 0x0c, 0x68, 0x01, 0x6a, 0x22, 0x01, 0xff, 0x6a, 0x26, 0x09, @@ -112,411 +111,376 @@ 0xff, 0x6a, 0x6c, 0x0c, 0x04, 0x14, 0x10, 0x31, 0x03, 0xa9, 0x18, 0x31, - 0x00, 0x65, 0xf0, 0x40, - 0xa8, 0x6a, 0x6a, 0x00, - 0x40, 0x3d, 0xe4, 0x68, - 0x04, 0x35, 0x6a, 0x00, - 0x00, 0x65, 0x72, 0x5b, - 0x80, 0x6a, 0xd4, 0x01, - 0x10, 0x36, 0xd8, 0x68, - 0x10, 0x36, 0x6c, 0x00, - 0x07, 0xac, 0x10, 0x31, - 0x05, 0xa3, 0x70, 0x30, - 0xff, 0x38, 0xf8, 0x68, - 0x80, 0x02, 0x04, 0x00, - 0x04, 0x35, 0x6a, 0x08, - 0x03, 0x69, 0x18, 0x31, - 0x22, 0x38, 0xc8, 0x28, - 0x01, 0x38, 0xfe, 0x60, - 0x02, 0x64, 0xc8, 0x00, - 0xff, 0x64, 0xf8, 0x09, - 0xff, 0x35, 0x26, 0x09, - 0x80, 0x02, 0x76, 0x69, - 0x10, 0x0c, 0x3a, 0x69, - 0x80, 0x94, 0x04, 0x79, - 0x01, 0x38, 0x30, 0x71, - 0x80, 0xea, 0x22, 0x61, - 0xef, 0x38, 0xc8, 0x18, - 0x80, 0x6a, 0xc8, 0x00, - 0x00, 0x65, 0x14, 0x49, - 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0xa1, 0x6a, 0x8a, 0x43, + 0xa1, 0x6a, 0x42, 0x43, 0xff, 0x51, 0xc8, 0x08, - 0xb9, 0x6a, 0x8a, 0x43, + 0xb9, 0x6a, 0x42, 0x43, 0xff, 0x90, 0xa4, 0x08, - 0xff, 0xba, 0x8e, 0x73, + 0xff, 0xba, 0x46, 0x73, 0xff, 0xba, 0x20, 0x09, 0xff, 0x65, 0xca, 0x18, - 0x00, 0x6c, 0x82, 0x63, + 0x00, 0x6c, 0x3a, 0x63, 0xff, 0x90, 0xca, 0x0c, 0xff, 0x6a, 0xca, 0x04, - 0x20, 0x36, 0xa2, 0x7b, - 0x00, 0x90, 0x76, 0x5b, - 0xff, 0x65, 0xa2, 0x73, - 0xff, 0x52, 0xa0, 0x73, + 0x20, 0x36, 0x5a, 0x7b, + 0x00, 0x90, 0x2e, 0x5b, + 0xff, 0x65, 0x5a, 0x73, + 0xff, 0x52, 0x58, 0x73, 0xff, 0xba, 0xcc, 0x08, 0xff, 0x52, 0x20, 0x09, 0xff, 0x66, 0x74, 0x09, 0xff, 0x65, 0x20, 0x0d, 0xff, 0xba, 0x7e, 0x0c, - 0x00, 0x6a, 0xce, 0x5c, + 0x00, 0x6a, 0x86, 0x5c, 0x0d, 0x6a, 0x6a, 0x00, - 0x00, 0x51, 0x2e, 0x44, - 0xff, 0x3f, 0xfc, 0x73, + 0x00, 0x51, 0xe6, 0x43, + 0xff, 0x3f, 0xb4, 0x73, 0xff, 0x6a, 0xa2, 0x00, - 0x00, 0x3f, 0x76, 0x5b, - 0xff, 0x65, 0xfc, 0x73, + 0x00, 0x3f, 0x2e, 0x5b, + 0xff, 0x65, 0xb4, 0x73, 0x20, 0x36, 0x6c, 0x00, - 0x20, 0xa0, 0xb6, 0x6b, + 0x20, 0xa0, 0x6e, 0x6b, 0xff, 0xb9, 0xa2, 0x0c, 0xff, 0x6a, 0xa2, 0x04, 0xff, 0x65, 0xa4, 0x08, 0xe0, 0x6a, 0xcc, 0x00, - 0x45, 0x6a, 0x22, 0x5c, + 0x45, 0x6a, 0xda, 0x5b, 0x01, 0x6a, 0xd0, 0x01, 0x09, 0x6a, 0xd6, 0x01, - 0x80, 0xeb, 0xc2, 0x7b, + 0x80, 0xeb, 0x7a, 0x7b, 0x01, 0x6a, 0xd6, 0x01, 0x01, 0xe9, 0xa4, 0x34, 0x88, 0x6a, 0xcc, 0x00, - 0x45, 0x6a, 0x22, 0x5c, + 0x45, 0x6a, 0xda, 0x5b, 0x01, 0x6a, 0x18, 0x01, 0xff, 0x6a, 0x1a, 0x09, 0xff, 0x6a, 0x1c, 0x09, 0x0d, 0x6a, 0x26, 0x01, - 0x00, 0x65, 0xc0, 0x5c, + 0x00, 0x65, 0x78, 0x5c, 0xff, 0x99, 0xa4, 0x0c, 0xff, 0x65, 0xa4, 0x08, 0xe0, 0x6a, 0xcc, 0x00, - 0x45, 0x6a, 0x22, 0x5c, + 0x45, 0x6a, 0xda, 0x5b, 0x01, 0x6a, 0xd0, 0x01, 0x01, 0x6a, 0xdc, 0x05, 0x88, 0x6a, 0xcc, 0x00, - 0x45, 0x6a, 0x22, 0x5c, + 0x45, 0x6a, 0xda, 0x5b, 0x01, 0x6a, 0x18, 0x01, 0xff, 0x6a, 0x1a, 0x09, 0xff, 0x6a, 0x1c, 0x09, 0x01, 0x6a, 0x26, 0x05, 0x01, 0x65, 0xd8, 0x31, 0x09, 0xee, 0xdc, 0x01, - 0x80, 0xee, 0xf2, 0x7b, + 0x80, 0xee, 0xaa, 0x7b, 0xff, 0x6a, 0xdc, 0x0d, 0xff, 0x65, 0x32, 0x09, 0x0a, 0x93, 0x26, 0x01, - 0x00, 0x65, 0xc0, 0x44, + 0x00, 0x65, 0x78, 0x44, 0xff, 0x37, 0xc8, 0x08, - 0x00, 0x6a, 0xb8, 0x5b, + 0x00, 0x6a, 0x70, 0x5b, 0xff, 0x52, 0xa2, 0x0c, - 0x01, 0x0c, 0x02, 0x7c, - 0x04, 0x0c, 0x02, 0x6c, + 0x01, 0x0c, 0xba, 0x7b, + 0x04, 0x0c, 0xba, 0x6b, 0xe0, 0x03, 0x06, 0x08, 0xe0, 0x03, 0x7a, 0x0c, 0xff, 0x8c, 0x10, 0x08, @@ -539,34 +503,34 @@ 0x00, 0x6c, 0xda, 0x24, 0xff, 0x65, 0xc8, 0x08, 0xe0, 0x6a, 0xcc, 0x00, - 0x41, 0x6a, 0x1e, 0x5c, + 0x41, 0x6a, 0xd6, 0x5b, 0xff, 0x90, 0xe2, 0x09, 0x20, 0x6a, 0xd0, 0x01, - 0x04, 0x35, 0x40, 0x7c, + 0x04, 0x35, 0xf8, 0x7b, 0x1d, 0x6a, 0xdc, 0x01, - 0xdc, 0xee, 0x3c, 0x64, - 0x00, 0x65, 0x56, 0x44, + 0xdc, 0xee, 0xf4, 0x63, + 0x00, 0x65, 0x0e, 0x44, 0x01, 0x6a, 0xdc, 0x01, 0x20, 0xa0, 0xd8, 0x31, 0x09, 0xee, 0xdc, 0x01, - 0x80, 0xee, 0x46, 0x7c, + 0x80, 0xee, 0xfe, 0x7b, 0x11, 0x6a, 0xdc, 0x01, - 0x50, 0xee, 0x4a, 0x64, + 0x50, 0xee, 0x02, 0x64, 0x20, 0x6a, 0xd0, 0x01, 0x09, 0x6a, 0xdc, 0x01, - 0x88, 0xee, 0x50, 0x64, + 0x88, 0xee, 0x08, 0x64, 0x19, 0x6a, 0xdc, 0x01, - 0xd8, 0xee, 0x54, 0x64, + 0xd8, 0xee, 0x0c, 0x64, 0xff, 0x6a, 0xdc, 0x09, - 0x18, 0xee, 0x58, 0x6c, + 0x18, 0xee, 0x10, 0x6c, 0xff, 0x6a, 0xd4, 0x0c, 0x88, 0x6a, 0xcc, 0x00, - 0x41, 0x6a, 0x1e, 0x5c, + 0x41, 0x6a, 0xd6, 0x5b, 0x20, 0x6a, 0x18, 0x01, 0xff, 0x6a, 0x1a, 0x09, 0xff, 0x6a, 0x1c, 0x09, 0xff, 0x35, 0x26, 0x09, - 0x04, 0x35, 0x84, 0x6c, + 0x04, 0x35, 0x3c, 0x6c, 0xa0, 0x6a, 0xca, 0x00, 0x20, 0x65, 0xc8, 0x18, 0xff, 0x6c, 0x32, 0x09, @@ -577,31 +541,31 @@ 0xff, 0x6c, 0x32, 0x09, 0xff, 0x6c, 0x32, 0x09, 0xff, 0x6c, 0x32, 0x09, - 0x00, 0x65, 0x6e, 0x64, + 0x00, 0x65, 0x26, 0x64, 0x0a, 0x93, 0x26, 0x01, - 0x00, 0x65, 0xc0, 0x44, + 0x00, 0x65, 0x78, 0x44, 0xa0, 0x6a, 0xcc, 0x00, 0xe8, 0x6a, 0xc8, 0x00, - 0x01, 0x94, 0x88, 0x6c, - 0x10, 0x94, 0x8a, 0x6c, - 0x08, 0x94, 0x9c, 0x6c, - 0x08, 0x94, 0x9c, 0x6c, - 0x08, 0x94, 0x9c, 0x6c, - 0x00, 0x65, 0xb0, 0x5c, + 0x01, 0x94, 0x40, 0x6c, + 0x10, 0x94, 0x42, 0x6c, + 0x08, 0x94, 0x54, 0x6c, + 0x08, 0x94, 0x54, 0x6c, + 0x08, 0x94, 0x54, 0x6c, + 0x00, 0x65, 0x68, 0x5c, 0x08, 0x64, 0xc8, 0x18, 0x00, 0x8c, 0xca, 0x18, - 0x00, 0x65, 0x92, 0x4c, - 0x00, 0x65, 0x88, 0x44, + 0x00, 0x65, 0x4a, 0x4c, + 0x00, 0x65, 0x40, 0x44, 0xf7, 0x93, 0x26, 0x09, - 0x08, 0x93, 0x9e, 0x6c, - 0x00, 0x65, 0xb0, 0x5c, + 0x08, 0x93, 0x56, 0x6c, + 0x00, 0x65, 0x68, 0x5c, 0x08, 0x64, 0xc8, 0x18, - 0x08, 0x64, 0xa0, 0x64, + 0x08, 0x64, 0x58, 0x64, 0xff, 0x6a, 0xd4, 0x0c, - 0x00, 0x65, 0xc0, 0x5c, - 0x00, 0x65, 0xb0, 0x5c, - 0x00, 0x65, 0xb0, 0x5c, - 0x00, 0x65, 0xb0, 0x5c, + 0x00, 0x65, 0x78, 0x5c, + 0x00, 0x65, 0x68, 0x5c, + 0x00, 0x65, 0x68, 0x5c, + 0x00, 0x65, 0x68, 0x5c, 0xff, 0x99, 0xda, 0x08, 0xff, 0x99, 0xda, 0x08, 0xff, 0x99, 0xda, 0x08, @@ -610,19 +574,19 @@ 0xff, 0x99, 0xda, 0x08, 0xff, 0x99, 0xda, 0x08, 0xff, 0x99, 0xda, 0x0c, - 0x08, 0x94, 0xc0, 0x7c, + 0x08, 0x94, 0x78, 0x7c, 0xf7, 0x93, 0x26, 0x09, - 0x08, 0x93, 0xc4, 0x6c, + 0x08, 0x93, 0x7c, 0x6c, 0xff, 0x6a, 0xd4, 0x0c, 0xff, 0x40, 0x74, 0x09, 0xff, 0x90, 0x80, 0x08, 0xff, 0x6a, 0x72, 0x05, - 0xff, 0x40, 0xdc, 0x64, - 0xff, 0x3f, 0xd4, 0x64, + 0xff, 0x40, 0x94, 0x64, + 0xff, 0x3f, 0x8c, 0x64, 0xff, 0x6a, 0xca, 0x04, 0xff, 0x3f, 0x20, 0x09, 0x01, 0x6a, 0x6a, 0x00, - 0x00, 0xb9, 0x2e, 0x5c, + 0x00, 0xb9, 0xe6, 0x5b, 0xff, 0xba, 0x7e, 0x0c, 0xff, 0x40, 0x20, 0x09, 0xff, 0xba, 0x80, 0x0c, @@ -630,12 +594,20 @@ 0xff, 0x90, 0x7e, 0x0c, }; +static int aic7xxx_patch15_func(struct aic7xxx_host *p); + +static int +aic7xxx_patch15_func(struct aic7xxx_host *p) +{ + return ((p->bugs & AHC_BUG_SCBCHAN_UPLOAD) != 0); +} + static int aic7xxx_patch14_func(struct aic7xxx_host *p); static int aic7xxx_patch14_func(struct aic7xxx_host *p) { - return ((p->bugs & AHC_BUG_SCBCHAN_UPLOAD) != 0); + return ((p->bugs & AHC_BUG_PCI_2_1_RETRY) != 0); } static int aic7xxx_patch13_func(struct aic7xxx_host *p); @@ -643,7 +615,7 @@ static int aic7xxx_patch13_func(struct aic7xxx_host *p) { - return ((p->features & AHC_CMD_CHAN) == 0); + return ((p->features & AHC_WIDE) != 0); } static int aic7xxx_patch12_func(struct aic7xxx_host *p); @@ -651,7 +623,7 @@ static int aic7xxx_patch12_func(struct aic7xxx_host *p) { - return ((p->bugs & AHC_BUG_PCI_2_1_RETRY) != 0); + return ((p->bugs & AHC_BUG_AUTOFLUSH) != 0); } static int aic7xxx_patch11_func(struct aic7xxx_host *p); @@ -659,7 +631,7 @@ static int aic7xxx_patch11_func(struct aic7xxx_host *p) { - return ((p->features & AHC_WIDE) != 0); + return ((p->features & AHC_ULTRA2) == 0); } static int aic7xxx_patch10_func(struct aic7xxx_host *p); @@ -667,7 +639,7 @@ static int aic7xxx_patch10_func(struct aic7xxx_host *p) { - return ((p->features & AHC_ULTRA2) == 0); + return ((p->features & AHC_CMD_CHAN) == 0); } static int aic7xxx_patch9_func(struct aic7xxx_host *p); @@ -675,7 +647,7 @@ static int aic7xxx_patch9_func(struct aic7xxx_host *p) { - return ((p->bugs & AHC_BUG_AUTOFLUSH) != 0); + return ((p->chip & AHC_CHIPID_MASK) == AHC_AIC7895); } static int aic7xxx_patch8_func(struct aic7xxx_host *p); @@ -772,59 +744,74 @@ { aic7xxx_patch8_func, 52, 7, 1 }, { aic7xxx_patch3_func, 60, 3, 1 }, { aic7xxx_patch7_func, 63, 2, 1 }, - { aic7xxx_patch7_func, 87, 1, 2 }, - { aic7xxx_patch0_func, 88, 1, 1 }, - { aic7xxx_patch7_func, 103, 1, 2 }, - { aic7xxx_patch0_func, 104, 2, 1 }, - { aic7xxx_patch7_func, 108, 84, 15 }, - { aic7xxx_patch9_func, 177, 1, 1 }, - { aic7xxx_patch9_func, 178, 4, 1 }, - { aic7xxx_patch0_func, 192, 72, 12 }, - { aic7xxx_patch1_func, 192, 1, 2 }, - { aic7xxx_patch0_func, 193, 2, 1 }, - { aic7xxx_patch1_func, 200, 1, 1 }, - { aic7xxx_patch1_func, 203, 3, 2 }, - { aic7xxx_patch0_func, 206, 5, 1 }, - { aic7xxx_patch1_func, 214, 1, 2 }, - { aic7xxx_patch0_func, 215, 3, 1 }, - { aic7xxx_patch1_func, 225, 14, 2 }, - { aic7xxx_patch0_func, 239, 9, 1 }, - { aic7xxx_patch1_func, 254, 2, 2 }, - { aic7xxx_patch0_func, 256, 4, 1 }, - { aic7xxx_patch1_func, 265, 3, 3 }, - { aic7xxx_patch10_func, 267, 1, 1 }, - { aic7xxx_patch0_func, 268, 5, 1 }, - { aic7xxx_patch10_func, 273, 1, 2 }, - { aic7xxx_patch0_func, 274, 9, 1 }, - { aic7xxx_patch11_func, 290, 1, 2 }, - { aic7xxx_patch0_func, 291, 1, 1 }, - { aic7xxx_patch4_func, 352, 1, 2 }, - { aic7xxx_patch0_func, 353, 1, 1 }, - { aic7xxx_patch2_func, 356, 1, 1 }, - { aic7xxx_patch1_func, 366, 3, 2 }, - { aic7xxx_patch0_func, 369, 5, 1 }, - { aic7xxx_patch11_func, 377, 1, 2 }, - { aic7xxx_patch0_func, 378, 1, 1 }, - { aic7xxx_patch5_func, 383, 1, 1 }, - { aic7xxx_patch10_func, 425, 15, 2 }, - { aic7xxx_patch12_func, 438, 1, 1 }, - { aic7xxx_patch1_func, 477, 7, 2 }, - { aic7xxx_patch0_func, 484, 8, 1 }, - { aic7xxx_patch1_func, 493, 4, 2 }, - { aic7xxx_patch0_func, 497, 6, 1 }, - { aic7xxx_patch1_func, 503, 4, 2 }, - { aic7xxx_patch0_func, 507, 3, 1 }, - { aic7xxx_patch13_func, 517, 10, 1 }, - { aic7xxx_patch1_func, 536, 22, 8 }, - { aic7xxx_patch10_func, 544, 4, 4 }, - { aic7xxx_patch0_func, 548, 7, 3 }, - { aic7xxx_patch14_func, 548, 5, 2 }, - { aic7xxx_patch0_func, 553, 2, 1 }, - { aic7xxx_patch0_func, 558, 50, 3 }, - { aic7xxx_patch12_func, 579, 17, 2 }, - { aic7xxx_patch0_func, 596, 4, 1 }, - { aic7xxx_patch13_func, 608, 4, 1 }, - { aic7xxx_patch5_func, 612, 2, 1 }, - { aic7xxx_patch5_func, 615, 9, 1 }, + { aic7xxx_patch7_func, 102, 1, 2 }, + { aic7xxx_patch0_func, 103, 2, 1 }, + { aic7xxx_patch7_func, 107, 2, 1 }, + { aic7xxx_patch9_func, 109, 1, 1 }, + { aic7xxx_patch10_func, 110, 2, 1 }, + { aic7xxx_patch7_func, 113, 1, 2 }, + { aic7xxx_patch0_func, 114, 1, 1 }, + { aic7xxx_patch1_func, 118, 1, 1 }, + { aic7xxx_patch1_func, 121, 3, 3 }, + { aic7xxx_patch11_func, 123, 1, 1 }, + { aic7xxx_patch0_func, 124, 5, 1 }, + { aic7xxx_patch7_func, 132, 1, 1 }, + { aic7xxx_patch9_func, 133, 1, 1 }, + { aic7xxx_patch10_func, 134, 3, 1 }, + { aic7xxx_patch7_func, 137, 3, 2 }, + { aic7xxx_patch0_func, 140, 2, 1 }, + { aic7xxx_patch7_func, 142, 5, 2 }, + { aic7xxx_patch0_func, 147, 3, 1 }, + { aic7xxx_patch7_func, 150, 1, 2 }, + { aic7xxx_patch0_func, 151, 2, 1 }, + { aic7xxx_patch1_func, 153, 15, 4 }, + { aic7xxx_patch11_func, 166, 1, 2 }, + { aic7xxx_patch0_func, 167, 1, 1 }, + { aic7xxx_patch0_func, 168, 10, 1 }, + { aic7xxx_patch7_func, 181, 1, 2 }, + { aic7xxx_patch0_func, 182, 2, 1 }, + { aic7xxx_patch7_func, 184, 18, 1 }, + { aic7xxx_patch1_func, 202, 3, 3 }, + { aic7xxx_patch7_func, 204, 1, 1 }, + { aic7xxx_patch0_func, 205, 4, 1 }, + { aic7xxx_patch7_func, 210, 2, 1 }, + { aic7xxx_patch7_func, 215, 13, 3 }, + { aic7xxx_patch12_func, 218, 1, 1 }, + { aic7xxx_patch12_func, 219, 4, 1 }, + { aic7xxx_patch1_func, 229, 3, 3 }, + { aic7xxx_patch11_func, 231, 1, 1 }, + { aic7xxx_patch0_func, 232, 5, 1 }, + { aic7xxx_patch11_func, 237, 1, 2 }, + { aic7xxx_patch0_func, 238, 9, 1 }, + { aic7xxx_patch13_func, 254, 1, 2 }, + { aic7xxx_patch0_func, 255, 1, 1 }, + { aic7xxx_patch4_func, 316, 1, 2 }, + { aic7xxx_patch0_func, 317, 1, 1 }, + { aic7xxx_patch2_func, 320, 1, 1 }, + { aic7xxx_patch1_func, 330, 3, 2 }, + { aic7xxx_patch0_func, 333, 5, 1 }, + { aic7xxx_patch13_func, 341, 1, 2 }, + { aic7xxx_patch0_func, 342, 1, 1 }, + { aic7xxx_patch5_func, 347, 1, 1 }, + { aic7xxx_patch11_func, 389, 15, 2 }, + { aic7xxx_patch14_func, 402, 1, 1 }, + { aic7xxx_patch1_func, 441, 7, 2 }, + { aic7xxx_patch0_func, 448, 8, 1 }, + { aic7xxx_patch1_func, 457, 4, 2 }, + { aic7xxx_patch0_func, 461, 6, 1 }, + { aic7xxx_patch1_func, 467, 4, 2 }, + { aic7xxx_patch0_func, 471, 3, 1 }, + { aic7xxx_patch10_func, 481, 10, 1 }, + { aic7xxx_patch1_func, 500, 22, 5 }, + { aic7xxx_patch11_func, 508, 4, 1 }, + { aic7xxx_patch7_func, 512, 7, 3 }, + { aic7xxx_patch15_func, 512, 5, 2 }, + { aic7xxx_patch0_func, 517, 2, 1 }, + { aic7xxx_patch10_func, 522, 50, 3 }, + { aic7xxx_patch14_func, 543, 17, 2 }, + { aic7xxx_patch0_func, 560, 4, 1 }, + { aic7xxx_patch10_func, 572, 4, 1 }, + { aic7xxx_patch5_func, 576, 2, 1 }, + { aic7xxx_patch5_func, 579, 9, 1 }, }; diff -U3 -rN scsi.save/aic7xxx.c scsi/aic7xxx.c --- scsi.save/aic7xxx.c Wed Feb 7 15:07:22 2001 +++ scsi/aic7xxx.c Wed Feb 7 23:18:29 2001 @@ -270,7 +270,7 @@ 0, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL, NULL }; -#define AIC7XXX_C_VERSION "5.2.2" +#define AIC7XXX_C_VERSION "5.2.3" #define NUMBER(arr) (sizeof(arr) / sizeof(arr[0])) #define MIN(a,b) (((a) < (b)) ? (a) : (b))