From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1616C00140 for ; Thu, 18 Aug 2022 08:00:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243987AbiHRIAU (ORCPT ); Thu, 18 Aug 2022 04:00:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52810 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243978AbiHRIAS (ORCPT ); Thu, 18 Aug 2022 04:00:18 -0400 Received: from out1.migadu.com (out1.migadu.com [91.121.223.63]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 371668050D for ; Thu, 18 Aug 2022 01:00:16 -0700 (PDT) Content-Type: text/plain; charset=utf-8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1660809614; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=rx2a0SfNDi1opj3mz7ReHR+gfYYq0rf6lV0w0JKT45s=; b=CgBP/vjkXrSV9tONNBZxXxt01X41B9cfBPakuv0gy9jMP771/oxkOS2DChxlcKEUBCpdsy Jchfuky/4rojGbFz24Mh+FSMVc2OnxdsUSjwz8mnXWcxFoENRqU+Ol9whopaLCzgWh2WAd S07y+1PZwzE0zwNxLdq5pE2I8KTHGTA= MIME-Version: 1.0 Subject: Re: [PATCH 4/6] mm: hugetlb_vmemmap: add missing smp_wmb() before set_pte_at() X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Muchun Song In-Reply-To: <7be98c64-88a1-3bee-7f92-67bb1f4f495b@huawei.com> Date: Thu, 18 Aug 2022 15:59:43 +0800 Cc: "Yin, Fengwei" , Andrew Morton , Mike Kravetz , Muchun Song , Linux MM , linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Message-Id: <3B1463C2-9DC4-43D0-93EC-2D2334A20502@linux.dev> References: <20220816130553.31406-1-linmiaohe@huawei.com> <20220816130553.31406-5-linmiaohe@huawei.com> <0EAF1279-6A1C-41FA-9A32-414C36B3792A@linux.dev> <019c1272-9d01-9d51-91a0-2d656b25c318@intel.com> <18adbf89-473e-7ba6-9a2b-522e1592bdc6@huawei.com> <9c791de0-b702-1bbe-38a4-30e87d9d1b95@intel.com> <931536E2-3948-40AB-88A7-E36F67954AAA@linux.dev> <7be98c64-88a1-3bee-7f92-67bb1f4f495b@huawei.com> To: Miaohe Lin X-Migadu-Flow: FLOW_OUT X-Migadu-Auth-User: linux.dev Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > On Aug 18, 2022, at 15:52, Miaohe Lin wrote: >=20 > On 2022/8/18 10:47, Muchun Song wrote: >>=20 >>=20 >>> On Aug 18, 2022, at 10:00, Yin, Fengwei = wrote: >>>=20 >>>=20 >>>=20 >>> On 8/18/2022 9:55 AM, Miaohe Lin wrote: >>>>>>> /* >>>>>>> * The memory barrier inside __SetPageUptodate makes = sure that >>>>>>> * preceding stores to the page contents become visible = before >>>>>>> * the set_pte_at() write. >>>>>>> */ >>>>>>> __SetPageUptodate(page); >>>>>> IIUC, the case here we should make sure others (CPUs) can see new = page=E2=80=99s >>>>>> contents after they have saw PG_uptodate is set. I think commit = 0ed361dec369 >>>>>> can tell us more details. >>>>>>=20 >>>>>> I also looked at commit 52f37629fd3c to see why we need a barrier = before >>>>>> set_pte_at(), but I didn=E2=80=99t find any info to explain why. = I guess we want >>>>>> to make sure the order between the page=E2=80=99s contents and = subsequent memory >>>>>> accesses using the corresponding virtual address, do you agree = with this? >>>>> This is my understanding also. Thanks. >>>> That's also my understanding. Thanks both. >>> I have an unclear thing (not related with this patch directly): Who = is response >>> for the read barrier in the read side in this case? >>>=20 >>> For SetPageUptodate, there are paring write/read memory barrier. >>>=20 >>=20 >> I have the same question. So I think the example proposed by Miaohe = is a little >> difference from the case (hugetlb_vmemmap) here. >=20 > Per my understanding, memory barrier in PageUptodate() is needed = because user might access the > page contents using page_address() (corresponding pagetable entry = already exists) soon. But for > the above proposed case, if user wants to access the page contents, = the corresponding pagetable > should be visible first or the page contents can't be accessed. So = there should be a data dependency > acting as memory barrier between pagetable entry is loaded and page = contents is accessed. > Or am I miss something? Yep, it is a data dependency. The difference between hugetlb_vmemmap and = PageUptodate() is that the page table (a pointer to the mapped page frame) is loaded by MMU = while PageUptodate() is loaded by CPU. Seems like the data dependency should be inserted between = the MMU access and the CPU access. Maybe it is hardware=E2=80=99s guarantee? >=20 > Thanks, > Miaohe Lin