Hi,

Some users have been sending init logs for Athlon kernels that
include PCI warning messages about the PCI cache line size
getting set incorrectly ... where the kernel thinks that the
right value is 16 bytes.  Since 64 bytes is the right number,
it's dangerous to enable MWI on such systems.

This patch stops trying to use MWI; it's a workaround for the
misbehavior of that PCI cacheline-setting code.  Please apply
to 2.5 and 2.4 trees.

- Dave