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Tue, 09 Jun 2026 02:15:15 -0700 (PDT) X-Received: by 2002:a05:622a:228e:b0:517:8999:6c4b with SMTP id d75a77b69052e-51795bbf777mr160227661cf.7.1780996514622; Tue, 09 Jun 2026 02:15:14 -0700 (PDT) Received: from [192.168.120.170] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-bf055307a35sm999893966b.52.2026.06.09.02.15.12 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 09 Jun 2026 02:15:13 -0700 (PDT) Message-ID: <3a0890b2-f9c3-439b-a392-fd13e3da850d@oss.qualcomm.com> Date: Tue, 9 Jun 2026 11:15:11 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 3/3] ASoC: qcom: lpass-va-macro: Add shikra compatible To: Mohammad Rafi Shaik , Srinivas Kandagatla , Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jaroslav Kysela , Takashi Iwai Cc: linux-arm-msm@vger.kernel.org, linux-sound@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260608172023.2965292-1-mohammad.rafi.shaik@oss.qualcomm.com> <20260608172023.2965292-4-mohammad.rafi.shaik@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260608172023.2965292-4-mohammad.rafi.shaik@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: VVdK-aRWpXLRbVoPIa1kpRrNpyrpmAuS X-Authority-Analysis: v=2.4 cv=EI42FVZC c=1 sm=1 tr=0 ts=6a27d9a3 cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=k1sLU3CPmF0_vJ11zi8A:9 a=QEXdDO2ut3YA:10 a=dawVfQjAaf238kedN5IG:22 X-Proofpoint-GUID: VVdK-aRWpXLRbVoPIa1kpRrNpyrpmAuS X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjA5MDA4NSBTYWx0ZWRfX2zy67WrnzpbO YUSfHaHBNbJqcXRkwqMvDgfdAhICZDCxFK1dxX84LARwQkRNtXA6z3bGBJY53uh2q1sL1BVOctF z0QCCpQ35phe//H3+TQcBUZGq5AWPf4vF18N4BQYtqPtGuRVI8OpsoNso8/rBa/t0549wiQ3OtH Wxydaz78pX6AGbEIkSUuLsD0rrHDk8wxkMs6JRw5T7GhXJPXDYhID1qKx99HIGmzza0MpKi38Ma pbF2H5oI5sfJF/rndxAjlkCwzTj9Q6i0rtGywQRQ0YckB0bys8VG0Eo30eVfC/8SNvOWZXFl8AR Go6Oqtp2yhSiIH8mbOzy5c1HpxCtzVy/L54os8EOWvljUX7iPmcUSrLYR6d9/5J4piZTIg7wqY/ Akx703rGA2wRD7V6Z8DOCF7G/hkk2TDjSfFHKXxqJM/ER0SBLwerrWG+dreiIFN76o4IrCDcypx sQ76ZdkMNprjlYChX3A== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-09_02,2026-06-09_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 adultscore=0 bulkscore=0 phishscore=0 suspectscore=0 malwarescore=0 priorityscore=1501 clxscore=1015 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606090085 On 6/8/26 7:20 PM, Mohammad Rafi Shaik wrote: > Add shikra specific VA macro data and register programming needed by > the LPASS codec v4.0 implementation. > > This adds a shikra regmap/default table covering the ADPT register > range, wires new match data flags (bypass FS control and ADPT block > presence), and enables the ADPT control programming path during TX > decimator bring-up. > > Signed-off-by: Mohammad Rafi Shaik > --- [...] > +/* ADPT control registers - Shikra adaptive filter blocks */ > +#define CDC_VA_CDC_ADPT0_ADPT_CTRL (0x0800) > +#define CDC_VA_CDC_ADPT0_ADPT_GAIN_0 (0x0804) > +#define CDC_VA_CDC_ADPT0_ADPT_GAIN_1 (0x0808) > +#define CDC_VA_CDC_ADPT0_DH_FSM_CTRL (0x080C) > +#define CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_0 (0x0810) > +#define CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_1 (0x0814) > +#define CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_2 (0x0818) > +#define CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_3 (0x081C) > +#define CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_4 (0x0820) > +#define CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_5 (0x0824) Please use lowercase hex and drop the parentheses [...] > +static const struct reg_default va_shikra_defaults[] = { > + /* VA macro */ > + { CDC_VA_CLK_RST_CTRL_MCLK_CONTROL, 0x00}, > + { CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00}, > + { CDC_VA_CLK_RST_CTRL_SWR_CONTROL, 0x00}, lowercase hex likewise, please keep a consistent space before the closing curly bracket [...] > + if (va->bypass_fs_control) > + regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL, > + 0x80, 0x80); regmap_set_bits() [...] > case SND_SOC_DAPM_POST_PMU: > + if (va->has_adpt_block) > + snd_soc_component_update_bits(comp, adapt_ctrl, 0xFF, 0x00); Can you define these magic numbers? [...] > + va->regmap = devm_regmap_init_mmio(dev, base, > + data->regmap_config ? data->regmap_config > + : &va_regmap_config); data->regmap_config ?: &va_regmap_config Konrad