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[77.252.46.238]) by smtp.gmail.com with ESMTPSA id f26-20020a056402069a00b0051e2670d599sm7112416edy.4.2023.09.05.04.59.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 05 Sep 2023 04:59:37 -0700 (PDT) Message-ID: <3a4988ae-97d7-66ee-5787-294b1204b1e2@linaro.org> Date: Tue, 5 Sep 2023 13:59:36 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.15.0 Subject: Re: [RFC PATCH 1/2] dt-bindings: PCI: ti,j721e-pci-*: Add "ti,syscon-pcie-refclk-out" property Content-Language: en-US To: Achal Verma , Vignesh Raghavendra , Lorenzo Pieralisi , Krzysztof Wilczy_ski , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley Cc: devicetree@vger.kernel.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20230905114816.2993628-1-a-verma1@ti.com> <20230905114816.2993628-2-a-verma1@ti.com> From: Krzysztof Kozlowski In-Reply-To: <20230905114816.2993628-2-a-verma1@ti.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 05/09/2023 13:48, Achal Verma wrote: > Added "ti,syscon-pcie-refclk-out" property to specify the ACSPCIE clock > buffer register offset in SYSCON, which would be used to enable serdes > reference clock output. > > Signed-off-by: Achal Verma > --- > .../bindings/pci/ti,j721e-pci-host.yaml | 53 +++++++++++++++++++ > 1 file changed, 53 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml > index a2c5eaea57f5..27bdc52282c4 100644 > --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml > +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml > @@ -44,6 +44,18 @@ properties: > - description: pcie_ctrl register offset within SYSCON > description: Specifier for configuring PCIe mode and link speed. > > + ti,syscon-pcie-refclk-out: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + items: > + - items: > + - description: Phandle to the SYSCON entry > + - description: lock2_kick0 register offset within SYSCON > + - description: lock2_kick1 register offset within SYSCON > + - description: acspcie_ctrl register offset within SYSCON > + - description: pcie_refclk_clksel register offset within SYSCON > + - description: clock source index to source ref clock > + description: Specifier for enabling ACSPCIe clock buffer for reference clock output. No, syscon is not a way to avoid creating clock/reset/power controllers. NAK. > power-domains: > maxItems: 1 > > @@ -99,6 +111,7 @@ required: > - reg > - reg-names > - ti,syscon-pcie-ctrl > + - ti,syscon-pcie-refclk-out So an ABI break? > - max-link-speed > - num-lanes > - power-domains > @@ -153,3 +166,43 @@ examples: > dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; > }; > }; > + > + - > + #include > + #include > + #include > + #include > + > + bus { > + #address-cells = <2>; > + #size-cells = <2>; > + > + pcie1_rc: pcie@2910000 { > + compatible = "ti,j784s4-pcie-host"; > + reg = <0x00 0x02910000 0x00 0x1000>, No need for new example. It's anyway wrongly formatted... Best regards, Krzysztof