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Sun, 31 May 2026 20:05:43 -0700 (PDT) X-Received: by 2002:a05:6a20:748d:b0:3a3:a55f:405d with SMTP id adf61e73a8af0-3b427c572e9mr9284033637.13.1780283142589; Sun, 31 May 2026 20:05:42 -0700 (PDT) Received: from [10.218.5.114] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c857fb0b31dsm6793462a12.32.2026.05.31.20.05.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 31 May 2026 20:05:42 -0700 (PDT) Message-ID: <3a623652-dfde-469e-af55-d4b54e3ee1d4@oss.qualcomm.com> Date: Mon, 1 Jun 2026 08:35:36 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/5] dt-bindings: clock: qcom: Add Qualcomm Shikra Display clock controller To: Dmitry Baryshkov Cc: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Loic Poulain , Ajit Pandey , Taniya Das , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260528-shikra-dispcc-gpucc-v2-0-953f246a0fbb@oss.qualcomm.com> <20260528-shikra-dispcc-gpucc-v2-2-953f246a0fbb@oss.qualcomm.com> <5nghgd3lt6vyewd3a7l4kahlxiidxdhgtu42tuyb7xeq62ztvu@tvclo336xtpi> <6d5fa33f-449e-4f22-b0d1-60a3a21a9907@oss.qualcomm.com> Content-Language: en-US From: Imran Shaik In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=BaDoFLt2 c=1 sm=1 tr=0 ts=6a1cf708 cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=TlunYbtFrR_dMKcEUgQA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-GUID: aFlR-Rpjbh-6YpLuUjgdxtDScOdJwixO X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjAxMDAyOCBTYWx0ZWRfXwR4yBdAqDYx+ rSnpQboGLeNaNko8tC8rwvHJmjCA2BTlINutZJru39IsDHVtoWzKxPGP9ST41egrKFzzI2xAim4 VKklceU2kBggqR73ckYNQhzukdyfT2YwrbbcN1NkzE3b9A5D/5jfRmACYn3ZuvrXWZRBQgqZYBW JpejPc7or2fXBAFY3OPVdg3wKqUG8ztpYB7cpNewy+EDGTj1V2MgNImhGePcZyn6Qzd/rLE9gsG bpY9WfI41bmcj5Pckn4dmtlsbCi3fjmgpC4cXVol0On/0R/h2A/iEHPrQqOsUGmBoiVHUOklo8O BSpUz+EG7YJoi4WSiJwjPbu9Nr25Rhogo/p5/u7WrosTilGvVRo72BQHM31JtZs6xjQ+zMU82bQ VOiRRdmo3+79didG9t4hlgrUs7KHhsfFLCUBZ17DtKcaIydS9S1nZCSJ5wHXZXGT9hTI+89S2i4 Yle56xt+vvTTReKZ3lg== X-Proofpoint-ORIG-GUID: aFlR-Rpjbh-6YpLuUjgdxtDScOdJwixO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-01_01,2026-05-28_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 clxscore=1015 phishscore=0 malwarescore=0 impostorscore=0 adultscore=0 priorityscore=1501 spamscore=0 lowpriorityscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606010028 On 29-05-2026 05:03 pm, Dmitry Baryshkov wrote: > On Fri, May 29, 2026 at 02:53:29PM +0530, Imran Shaik wrote: >> >> >> On 28-05-2026 07:14 pm, Dmitry Baryshkov wrote: >>> On Thu, May 28, 2026 at 03:37:03PM +0530, Imran Shaik wrote: >>>> The Qualcomm Shikra Display clock controller reuses the QCM2290 DISPCC, >>>> but has minor differences with the number of input clocks. Update the >>>> existing QCM2290 DISPCC bindings using conditional schema so that the >>>> QCM2290 requirements remain unchanged while accommodating the additional >>>> clocks required for Shikra. >>> >>> According to the IPcat, display clock controller also has (unused) >>> inputs for the DSI1. Please extend the ABI for Agatti, then extend add >>> Shikra. >>> >> >> Sure, will add the DSI1 to Agatti as well. Since we are extending the ABI >> for Agatti, I will remove the clock-names from the bindings > > Why? > >> and update the >> DISPCC driver to use the indices-based approach instead. >> >> With these updates, the bindings, driver, and Agatti DT must be picked >> together to avoid any functional issues or ABI breakage. I will explicitly >> document these details in the commit message in the next series. > > Well, no. DT comes through a separate tree anyway. Be sure that the > updated driver works with the old DT. Also make sure to not change the > order of the clocks, you can't break the ABI. > Sure, I’ll keep the clock-names property and only append new clocks at the end without changing the current order. Thanks, Imran