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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b9832f440e7sm615146366b.3.2026.03.24.03.18.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 24 Mar 2026 03:18:33 -0700 (PDT) Message-ID: <3a71adbc-b06c-4c04-b539-abb56e4b1c6d@oss.qualcomm.com> Date: Tue, 24 Mar 2026 11:18:30 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 14/16] drm/msm/a8xx: Preemption support for A840 To: Akhil P Oommen , Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , Antonino Maniscalco , Connor Abbott , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org References: <20260324-a8xx-gpu-batch2-v1-0-fc95b8d9c017@oss.qualcomm.com> <20260324-a8xx-gpu-batch2-v1-14-fc95b8d9c017@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260324-a8xx-gpu-batch2-v1-14-fc95b8d9c017@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=VvUuwu2n c=1 sm=1 tr=0 ts=69c264fb cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=n4QsoBDMxz4R0sOL5fcA:9 a=QEXdDO2ut3YA:10 a=uxP6HrT_eTzRwkO_Te1X:22 X-Proofpoint-GUID: aQeWYLc-bLEMActlGZf_w1OHco0u9GvR X-Proofpoint-ORIG-GUID: aQeWYLc-bLEMActlGZf_w1OHco0u9GvR X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzI0MDA4MiBTYWx0ZWRfX0fznWpRFXqsr 2P9ay03J1qjrs8csNRBZeprybEYzRsW7aDCo5y57FkxbOX+/a1dFdRZ8zLCligMNLr7xC1yxPLn i1ailjWugh1CVR5aCNtBcgFFvwSghzA5yDnL7IjeLyORaB+iRreY3rlC27HbJXFV6NVxMbXiT1Q JIaLr5h5Rw4zIexBLBqYYx4eI2pQ+CyRUCu9A81Da0Iyl1ScZgm/SxXiVEa14lXWfMvu9Wy4Jm7 GdvAQHiOAHFZEEYV7jRt2MZF0mqbt5dGSuxYk0obZZl+GEvb1yM0WRCPyRZmvJYggSwFQWSfxZ0 63TS07E9XmwXffH6UUws639WrGxp2caRtGvPG0YKNT5L7nfA8eD15dnYw6IUYI21P3CgnMbtrhJ MWTjaVVMyH+mw2TdWIZ+xSd+b2em/rEvqX2oNQX3wEdrGCiHBAHMCV7kDLHZDtyeeM/azTytFas 10WwBgTPALOLMY77n3A== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-24_02,2026-03-23_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 malwarescore=0 spamscore=0 adultscore=0 lowpriorityscore=0 impostorscore=0 bulkscore=0 clxscore=1015 priorityscore=1501 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603240082 On 3/23/26 9:12 PM, Akhil P Oommen wrote: > The programing sequence related to preemption is unchanged from A7x. But > there is some code churn due to register shuffling in A8x. So, split out > the common code into a header file for code sharing and add/update > additional changes required to support preemption feature on A8x GPUs. > > Finally, enable the preemption quirk in A840's catalog to enable this > feature. > > Signed-off-by: Akhil P Oommen > --- [...] > + /* ... and after*/ ultra nit: space before comment end marker, please [...] > +static int a8xx_preempt_start(struct msm_gpu *gpu) > +{ > + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); > + struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); > + struct msm_ringbuffer *ring = gpu->rb[0]; > + > + if (gpu->nr_rings <= 1) Can this ever be < 1? > +static void a8xx_preempt_keepalive_vote(struct msm_gpu *gpu, bool on) > +{ > + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); > + struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); > + > + if (adreno_has_gmu_wrapper(adreno_gpu)) > + return; Are we going to have any a8xx+gmuwrapper? Konrad