Re: [PATCH v3 1/2] dt-bindings: timer: mti,gcru

[Aleksa Paunovic <aleksa.paunovic@htecgroup.com>]

On 24. 4. 25. 08:24, Krzysztof Kozlowski wrote:
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> 
> On 23/04/2025 14:14, Aleksa Paunovic wrote:
>> HTEC Public
> 
> Fix your email systems or use b4 relay.
> 
> 
> <form letter>
> Please use scripts/get_maintainers.pl to get a list of necessary people
> and lists to CC (and consider --no-git-fallback argument, so you will
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> entries. Therefore please be sure you base your patches on recent Linux
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> Tools like b4 or scripts/get_maintainer.pl provide you proper list of
> people, so fix your workflow. Tools might also fail if you work on some
> ancient tree (don't, instead use mainline) or work on fork of kernel
> (don't, instead use mainline). Just use b4 and everything should be
> fine, although remember about `b4 prep --auto-to-cc` if you added new
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> </form letter>
>  
Thank you for the tips. Will be using b4 relay in the future, starting with v4 linked at [1].

[1]
https://lore.kernel.org/linux-riscv/20250514-riscv-time-mmio-v4-0-cb0cf2922d66@htecgroup.com/

Best regards,
Aleksa Paunovic
>>
>> Add dt-bindings for the GCR.U memory mapped timer device for RISC-V
>> platforms. The GCR.U memory region contains shadow copies of the RISC-V
>> mtime register and the hrtime Global Configuration Register.
>>
>> Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
>> ---
>>  .../devicetree/bindings/timer/mti,gcru.yaml   | 47 +++++++++++++++++++
>>  1 file changed, 47 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/timer/mti,gcru.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/timer/mti,gcru.yaml b/Documentation/devicetree/bindings/timer/mti,gcru.yaml
>> new file mode 100644
>> index 000000000000..6555dbab402e
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/timer/mti,gcru.yaml
>> @@ -0,0 +1,47 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/timer/mti,gcru.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: GCR.U timer device for RISC-V platforms
>> +
>> +maintainers:
>> +  - Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
>> +
>> +description:
>> +  The GCR.U memory region contains memory mapped shadow copies of
>> +  mtime and hrtime Global Configuration Registers,
>> +  which software can choose to make accessible from user mode.
>> +
>> +select:
>> +  properties:
>> +    compatible:
>> +      contains:
>> +        const: mti,gcru
>> +
>> +  required:
>> +    - compatible
> 
> Drop select, why do you need it?
> 
>> +
>> +properties:
>> +  compatible:
>> +    const: mti,gcru
>> +
>> +  reg:
>> +    items:
>> +      - description: Read-only shadow copy of the RISC-V mtime register.
>> +      - description: Read-only shadow copy of the high resolution timer register.
>> +
>> +required:
>> +  - compatible
>> +  - reg
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> +  - |
>> +    gcru: timer@1617F000 {
> 
> Lower-case hex in DTS, always. See DTS coding style.
> 
> Best regards,
> Krzysztof