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Wed, 17 Jun 2026 04:42:48 -0700 (PDT) X-Received: by 2002:a05:620a:d8b:b0:90f:7ce2:3019 with SMTP id af79cd13be357-91dbd008667mr273170685a.7.1781696568174; Wed, 17 Jun 2026 04:42:48 -0700 (PDT) Received: from [192.168.120.170] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-bfdb44209f0sm788394666b.6.2026.06.17.04.42.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 17 Jun 2026 04:42:47 -0700 (PDT) Message-ID: <3ab3ccfc-1fdc-4176-b073-1f31e2c88c6a@oss.qualcomm.com> Date: Wed, 17 Jun 2026 13:42:44 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/4] dt-bindings: mtd: qcom,nandc: Add MDM9607 QPIC NAND controller To: Stephan Gerhold , Miquel Raynal , Manivannan Sadhasivam , Kathiravan Thirumoorthy Cc: Krzysztof Kozlowski , Manivannan Sadhasivam , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-mtd@lists.infradead.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260608-qcom-nandc-mdm9607-v1-0-4639a0492274@linaro.org> <20260608-qcom-nandc-mdm9607-v1-1-4639a0492274@linaro.org> <20260609-quirky-rat-of-criticism-aea1fe@quoll> <87mrx4b164.fsf@bootlin.com> <35c7513b-6aea-48cf-aea8-da8604616601@oss.qualcomm.com> <87o6hk9i29.fsf@bootlin.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: xedd91Bqopu7wVHm78s8shC7JMV2RvFL X-Authority-Analysis: v=2.4 cv=IeC3n2qa c=1 sm=1 tr=0 ts=6a328839 cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=FDdbgDo1gx5wMt_MktwA:9 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwNjE3MDExMCBTYWx0ZWRfX2ChkYs7ktsDf OBwvdZARA5O2kHti5L/1+jif3MADYdq6IP4hdbMVWqn0Q6CDbXoGmXtSS6rHGnGaylUA1ng1i3U 3ME9bZe3hrW9Hf/7OtF+X6W0J0W7+M4= X-Proofpoint-ORIG-GUID: xedd91Bqopu7wVHm78s8shC7JMV2RvFL X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjE3MDExMCBTYWx0ZWRfX9u7cSUpmCou0 XOIv00gtLxWVZBwDc4BOsMJJL+Jqez1EFmFyfyVaqy2Eg4gAP84Xho6yRDdaZgTwcQvlb86WHQc cguD2KhDl8rFVYr2sV9Si805iemQoquGtXRiDVqFSVAjGqWKGwtRRPFtuTqIc4PZbK89PquZ9vp 6hZZdyst8HdA3qZvrPjDKOgY3Bpkr51S8HcXoujEj5NVVaJy00R2o+4WvcAJefInMS8mlht6djj AM3YEO1ULxqZ7ZRpQTLJGdnPEsIy6O/KL0RHR/IrD0az58PA3MJwtOZgVx4rQeqJxt4qduLqRVf h3W9oUk4h3uXunwD4JdJvaUMOZ07NUTUE8/3WG2DNDB+lMGx5kDatiDA2UxcmXJSz90CnIKVtkl AslCaGix1JO8wotFQxPDSk/HULSgskmOOV0ZB9RUXl6HCZ1M0MEpyBkIh91mfPszolF+0F/p9HV NRFzJiiJfX69TGKIkYQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-17_01,2026-06-16_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 adultscore=0 malwarescore=0 spamscore=0 clxscore=1015 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606170110 On 6/9/26 12:02 PM, Stephan Gerhold wrote: > On Tue, Jun 09, 2026 at 11:30:54AM +0200, Miquel Raynal wrote: >> On 09/06/2026 at 11:08:03 +02, Stephan Gerhold wrote: >> >>> On Tue, Jun 09, 2026 at 11:01:18AM +0200, Konrad Dybcio wrote: >>>> On 6/9/26 10:55 AM, Konrad Dybcio wrote: >>>>> On 6/9/26 10:10 AM, Stephan Gerhold wrote: >>>>>> On Tue, Jun 09, 2026 at 09:52:51AM +0200, Miquel Raynal wrote: >>>>>>>>> On MDM9607, there is only a single controllable clock for the NAND >>>>>>>>> controller (RPM_SMD_QPIC_CLK). The same situation also applies e.g. for >>>>>>>>> qcom,sdx55-nand, but the corresponding device tree (qcom-sdx55.dtsi) works >>>>>>>>> around that by assigning a dummy clock (&nand_clk_dummy) to the second >>>>>>>>> clock ("aon") that is required by the dt-bindings. This is not really >>>>>>>>> useful, so avoid doing that for new platforms by excluding the second "aon" >>>>>>>>> clock entry in the dt-bindings. >>>>>>>> >>>>>>>> Reviewed-by: Krzysztof Kozlowski >>>>>>> >>>>>>> What is the problem in giving twice the same clock? If this is what is >>>>>>> done in the hardware routing, I do not see the reason for more >>>>>>> complexity in the binding? >>>>>>> >>>>>> >>>>>> I had that in my first draft for this series, but this would be wrong >>>>>> IMO. I suspect there is no QPIC/NAND related "aon" (always-on) clock on >>>>>> this platform at all. I'm not sure about MDM9607 in particular (maybe >>>>>> someone from Qualcomm can confirm), but a similar platform I was looking >>>>>> into at some point actually had *3* separate clocks for QPIC in the >>>>>> hardware and none of them were called "aon" ... >>>>> >>>>> gcc_qpic_ahb_clk (50/100/133.(3) MHz sourced from PCNoC_bfdcd_clk_src) >>>>> gcc_qpic_clk (likewise, sourced from qpic_clk_src which is sourced >>>>> from GPLLs) >>>>> gcc_qpic_system_clk (32 KHz) >>>>> >>>>> No clock containing the substring 'aon' in its name on this platform >>>> >>>> Looking at SDX65, perhaps the 32 Khz clock is the "aon" one after all.. >>>> The NAND documentation says >>>> >>>> CC_QPIC_SYSTEM_CLK - Always-on timeout clock (32 KHz) >>>> >>> >>> Thanks for looking this up. >>> >>> IMO, if we want to describe the actual hardware routing, we should >>> describe all 3 clocks and assign all of them to RPM_SMD_QPIC_CLK for >>> MDM9607). >> >> Sounds more accurate to me. >> >>> The resulting diff would be basically the same as this patch just >>> inversed (3 clocks for MDM9607+SDX(?) and 2 clocks for the IPQ* SoCs. >> >> Diff would not be simpler but more accurate. So if we go for a >> modification of the bindings, I would prefer that path. >> > > IMO the result wouldn't be much more accurate from the perspective of > the kernel. If we assign RPM_SMD_QPIC_CLK to all 3 clocks we would be > effectively saying "there is a single clock with a single rate that is > sourcing 'core', 'ahb' and 'system'(/'aon')". But in reality, these are > 3 separate clock domains with separate rates, as shown by Konrad above. > > We could try defining dummy clocks like the &nand_clk_dummy in > qcom-sdx55.dtsi, but this isn't very accurate either. Presumably, all of > these clocks are toggled by RPM_SMD_QPIC_CLK. So if we define a dummy > clock for 'ahb', then enabling that clock without also enabling the > non-dummy 'core' (RPM_SMD_QPIC_CLK) will do nothing. I can't find a good answer for what RPM_SMD_QPIC_CLK controls, maybe +Mani or +Kathiravan know where to look Konrad > > At the end, the truth for the OS/kernel running on this hardware is that > it can only see the 'core' clock (with the option to change its rate). > All others are invisible, with no way to influence or check the status, > so pretending that we have separate resources for them doesn't really > make things more accurate in my opinion. > > But yeah, let's leave the decision up to Krzysztof. I'm happy to change > this patch as needed as long it works at the end. :-)