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Mon, 26 Oct 2026 09:35:54 +0000 (GMT) Received: from [192.168.1.44] (unknown [106.210.136.40]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20261026093552eusmtip250daa3502a30759f756704eb1d885faf~iCq-4FCDh0127501275eusmtip2b; Mon, 26 Oct 2026 09:35:52 +0000 (GMT) Message-ID: <3aee23e0-1a9e-4649-b9ac-72012f9feaa6@samsung.com> Date: Mon, 26 Oct 2026 10:35:52 +0100 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 19/21] phy: starfive: Add jh7110-inno-hdmi-phy driver To: Vinod Koul Cc: Manivannan Sadhasivam , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrzej Hajda , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Andy Yan , Philipp Zabel , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Heiko Stuebner , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Dominique Belhachemi , Brian Masney , Jerome Brunet , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, Marek Szyprowski , Maud Spierings , Graham Markall , Icenowy Zheng , Chaoyi Chen , Joshua Peisach , =?UTF-8?Q?Uwe_Kleine-K=C3=B6nig?= Content-Language: en-US From: Michal Wilczynski In-Reply-To: Content-Transfer-Encoding: 7bit X-CMS-MailID: 20261026093554eucas1p27ee3526a6b2fdb9f2c6c35e69ac09fe9 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20260929103245eucas1p1349d00810646fbf0149f1361534c23ac X-EPHeader: CA X-CMS-RootMailID: 20260929103245eucas1p1349d00810646fbf0149f1361534c23ac References: <20260929-jh7110-clean-send-v5-0-82b4d8e3c6c7@samsung.com> <20260929-jh7110-clean-send-v5-19-82b4d8e3c6c7@samsung.com> On 10/3/26 16:25, Vinod Koul wrote: > On 29-09-26, 12:31, Michal Wilczynski wrote: >> Add the HDMI PHY driver for the StarFive JH7110. >> >> This driver binds to the starfive,jh7110-inno-hdmi-phy node and >> gets its regmap from the parent. It has no dependencies on voutcrg, only >> on its reference oscillator (xin24m), which breaks the probe-time >> circular dependency. >> >> This driver provides two main functions: >> - Clock Provider: It registers clk_ops to provide the variable pixel >> clock. The .set_rate operation configures the Pre-PLL registers >> (0x1a0+) based on the requested rate. >> >> - PHY Provider: It registers phy_ops for the controller. The .power_on >> op configures and enables the Post-PLL and other analog blocks (BIAS, >> LDO, Serializer, etc.). >> >> The clock ops reach registers in the window shared with the HDMI >> controller, and access to that window is gated by the controller's >> system clock, which only the sibling controller driver holds. The clock >> framework walks every registered clock regardless of which drivers have >> bound, so deliberately do not implement .is_prepared, which lets the >> framework fall back to the software prepare count, and return the cached >> rate from .recalc_rate whenever the clock is not prepared. Without this, >> clk_disable_unused() reads a PHY register with that clock gated and the >> resulting stalled bus transaction wedges the CPU hard enough that it >> stops responding to NMIs. It is reproducible by building the bridge >> driver as a module so that the controller has not bound by then. >> >> The JH7110 instantiates the same Innosilicon IP as the Rockchip RK3328, >> with the PHY register block shifted by 0x100 because it sits behind the >> HDMI controller in the shared register space. The pre-PLL programming >> therefore comes from the common Innosilicon helpers; this driver adds >> the JH7110 pixel clock table, the post-PLL and the analog configuration. >> >> Co-developed-by: Dominique Belhachemi >> Signed-off-by: Dominique Belhachemi >> Signed-off-by: Michal Wilczynski >> --- >> drivers/phy/starfive/Kconfig | 20 + >> drivers/phy/starfive/Makefile | 1 + >> drivers/phy/starfive/phy-jh7110-inno-hdmi.c | 582 ++++++++++++++++++++++++++++ >> 3 files changed, 603 insertions(+) >> >> + STF_INNO_TMDS_D1_DRIVER_EN | \ >> + STF_INNO_TMDS_D0_DRIVER_EN) >> + >> +/* REG: 0x1b4 */ >> +#define STF_INNO_LDO_CONTROL 0x1b4 >> +#define STF_INNO_LDO_ENABLE (BIT(2) | BIT(1) | BIT(0)) >> + >> +/* REG: 0x1be */ >> +#define STF_INNO_SERIALIER_CONTROL 0x1be >> +#define STF_INNO_SERIALIER_ENABLE (BIT(6) | BIT(5) | BIT(4) | BIT(0)) >> + >> +/* REG: 0x1cc */ >> +#define STF_INNO_RX_CONTROL 0x1cc >> +#define STF_INNO_RX_ENABLE (BIT(3) | BIT(2) | BIT(1) | BIT(0)) >> + >> +/* >> + * These tables are copied from the monolithic driver. >> + * They match the Rockchip PHY driver tables. >> + */ >> + >> +struct post_pll_config { >> + unsigned long tmdsclock; >> + u8 prediv; >> + u16 fbdiv; >> + u8 postdiv; >> + u8 post_div_en; >> +}; >> + >> +static const struct inno_hdmi_phy_pre_pll_config pre_pll_cfg_table[] = { >> + { 25175000, 25175000, 1, 100, 2, 3, 3, 12, 3, 3, 4, 0, 0xF55555 }, > > lower case hex values, here and everywhere else please Sure will fix this. > Best regards, -- Michal Wilczynski