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Mon, 27 Jul 2026 06:56:57 -0700 (PDT) X-Received: by 2002:ac8:5981:0:b0:517:5d21:9899 with SMTP id d75a77b69052e-529a85f9b2emr122120981cf.5.1785160616824; Mon, 27 Jul 2026 06:56:56 -0700 (PDT) Received: from [192.168.120.193] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-69fb50bcfdcsm2876913a12.3.2026.07.27.06.56.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 27 Jul 2026 06:56:56 -0700 (PDT) Message-ID: <3b0166c0-e1e7-4746-bcb9-ef78b9a86c8c@oss.qualcomm.com> Date: Mon, 27 Jul 2026 15:56:53 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v7 2/6] phy: qcom: qmp-pcie: Add QMP PCIe Multi-PHY driver To: Qiang Yu , Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam , Philipp Zabel , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam References: <20260724-glymur_linkmode_0724-v7-0-65c8469c6b65@oss.qualcomm.com> <20260724-glymur_linkmode_0724-v7-2-65c8469c6b65@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260724-glymur_linkmode_0724-v7-2-65c8469c6b65@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: zP8LB7Ja5Xu-2EJdlO4dg312oAGOXWsD X-Authority-Analysis: v=2.4 cv=cJjQdFeN c=1 sm=1 tr=0 ts=6a6763aa cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=fUhyWj0mt7oSvnhCvGYA:9 a=QEXdDO2ut3YA:10 a=uxP6HrT_eTzRwkO_Te1X:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzI3MDEzMyBTYWx0ZWRfX2KKnG3IdhPeG FJiQr1axnJ744GWdXdoz043i/2k7tsN4fiKZIKjbJJq7fXD9XFBYgA+kMNVOAssgn5hibeMdceC P4DRR5YlqSTf8mpQJZi/3S6r/wEp1ZY= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzI3MDEzMyBTYWx0ZWRfXxlYRVGiBLX5p pbdfb249N0xGDias5WGk4Etg5vHoNN0VEvqg59cP0XQ55psOUGRVW2tvL308hc6nhBDN9Gv0Oza zFknenWqaZsGBvP1hkmEqXJ7adbr4FgQLvZ/FW2xNnpjTaxyMe+AbOqm2s++/f9lOTUsxi+U9Av smLXFxYkmbD40+tHxCruesDgtla6yLvWxqFgexz1tDKKJshGRAZlek0HfMcj+4ewmDytWm4Mp61 uR57+npEfnJPF5xkT4CTRSieWiJAwr7iex7gBLgC7mpMnqKUL+RvZq7INSroWclhlJHI3u06Tfg t9RXhEMoqeGF5MbkdLjvgD1teW8F15gTBOyQg7QSbquqGFY6a0Y24+4oeLm1vCOX3cq9rEZ0M4k d3/+DYQCVip+s9eFqwbb0Wafw38EUiQu6UMlhxSkCE5w0/xZIVYN37G8RGyQpzORWrxLHqmNFnW XYlb9lW+bMqntMqHLWA== X-Proofpoint-GUID: zP8LB7Ja5Xu-2EJdlO4dg312oAGOXWsD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-27_04,2026-07-24_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 spamscore=0 adultscore=0 suspectscore=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 bulkscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607270133 On 7/24/26 12:01 PM, Qiang Yu wrote: > Some QMP PCIe PHY hardware blocks support multiple link topologies (e.g. > x8 or x4+x4) selected via a TCSR register. The existing single-instance > QMP PCIe PHY driver has no way to model this: it assumes a single cfg per > DT node and instantiates exactly one PHY. > > Add a dedicated driver for this class of PHY. Match data carries a > per-mode cfg table; qmp_pcie_multiphy_probe() reads the current link > mode from the TCSR register pointed to by "qcom,link-mode", looks up the > corresponding cfg array, and instantiates one qmp_pcie per sub-PHY > required by that link mode, registering the clock and #phy-cells = <1> phy > providers so consumers can address individual sub-PHYs by index. > > The driver inherits the phy setting and link-mode programmed by firmware, > so only the no_csr reset is used and no phy setting tables are provided. > > Add the first match data and compatible, qcom,glymur-qmp-gen5x8-pcie-phy, > for the Glymur Gen5 PCIe PHY that can bifurcate into two x4 links or > operate as a single x8 link. > > Reviewed-by: Manivannan Sadhasivam > Signed-off-by: Qiang Yu > --- This looks really good, couple of follow-up improvement suggestions [...] > +static const char * const glymur_pciephy_a_reg_l[] = { > + "port_a", > +}; > + > +static const char * const glymur_pciephy_b_reg_l[] = { > + "port_b", > +}; > + > +static const char * const glymur_pciephy_reg_l[] = { > + "port_a", "port_b", > +}; I think we could construct these names at the call sites, with essentially something like for (i = 0; i < qmp->num_ports; i++) { sprintf(buf, "port_%c\n", 'a' + i); } (is that too cheesy?) [...] > +err_power_off: > + while (--i >= 0) > + pm_runtime_put(qmp->pd_devs[i]); This probably can stay non-sync > + > + return ret; > +} > + > +static void qmp_pcie_pd_power_off(struct qmp_pcie *qmp) > +{ > + const struct qmp_phy_cfg *cfg = qmp->cfg; > + int i; > + > + for (i = cfg->num_pds - 1; i >= 0; i--) > + pm_runtime_put(qmp->pd_devs[i]); This should probably be _sync() as phy init/exit may be called in quick succession [...] > +static int __phy_pipe_clk_register(struct device *dev, struct device_node *np, > + int idx, struct clk_fixed_rate *fixed) > +{ > + struct clk_init_data init = { }; > + int ret; > + > + ret = of_property_read_string_index(np, "clock-output-names", idx, > + &init.name); > + if (ret) { > + dev_err(dev, "%pOFn: No clock-output-names\n", np); > + return ret; > + } > + > + init.ops = &clk_fixed_rate_ops; > + > + if (!fixed->fixed_rate) > + fixed->fixed_rate = 125000000; I think this always happens to be true in this driver [...] > + num_pipe_outputs = of_property_count_strings(np, "clock-output-names"); > + if (num_pipe_outputs < 0) > + num_pipe_outputs = 1; This can't happen (clock-output-names is required via bindings) [...] > +static int qmp_pcie_read_link_mode(struct device *dev, unsigned int *link_mode) > +{ > + struct regmap *map; > + unsigned int args[1]; > + int ret; > + > + map = syscon_regmap_lookup_by_phandle_args(dev->of_node, "qcom,link-mode", > + ARRAY_SIZE(args), args); > + if (IS_ERR(map)) > + return PTR_ERR(map); > + > + ret = regmap_read(map, args[0], link_mode); > + if (ret) > + return ret; > + > + return 0; ret = xxx() if (ret) return ret; return 0; can be collapsed to simply return regmap_read() with or without all that, Reviewed-by: Konrad Dybcio Konrad