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([2a01:e0a:3d9:2080:cb6f:4c33:aee:566b]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b778eba0e6sm8409045f8f.25.2025.07.28.03.10.15 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 28 Jul 2025 03:10:16 -0700 (PDT) Message-ID: <3b4a4517-fe86-4be0-8b1b-99401fe719c6@linaro.org> Date: Mon, 28 Jul 2025 12:10:15 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: neil.armstrong@linaro.org Reply-To: Neil Armstrong Subject: Re: [PATCH] arm64: dts: qcom: sm8650: Sort nodes by unit address To: Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250727193652.4029-2-krzysztof.kozlowski@linaro.org> Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKk5laWwgQXJtc3Ryb25nIDxuZWlsLmFybXN0cm9uZ0BsaW5hcm8ub3JnPsLAkQQTAQoA OwIbIwULCQgHAwUVCgkICwUWAgMBAAIeAQIXgBYhBInsPQWERiF0UPIoSBaat7Gkz/iuBQJk Q5wSAhkBAAoJEBaat7Gkz/iuyhMIANiD94qDtUTJRfEW6GwXmtKWwl/mvqQtaTtZID2dos04 YqBbshiJbejgVJjy+HODcNUIKBB3PSLaln4ltdsV73SBcwUNdzebfKspAQunCM22Mn6FBIxQ GizsMLcP/0FX4en9NaKGfK6ZdKK6kN1GR9YffMJd2P08EO8mHowmSRe/ExAODhAs9W7XXExw UNCY4pVJyRPpEhv373vvff60bHxc1k/FF9WaPscMt7hlkbFLUs85kHtQAmr8pV5Hy9ezsSRa GzJmiVclkPc2BY592IGBXRDQ38urXeM4nfhhvqA50b/nAEXc6FzqgXqDkEIwR66/Gbp0t3+r yQzpKRyQif3OwE0ETVkGzwEIALyKDN/OGURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYp QTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXMcoJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+ SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hiSvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY 4yG6xI99NIPEVE9lNBXBKIlewIyVlkOaYvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoM Mtsyw18YoX9BqMFInxqYQQ3j/HpVgTSvmo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUX oUk33HEAEQEAAcLAXwQYAQIACQUCTVkGzwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfn M7IbRuiSZS1unlySUVYu3SD6YBYnNi3G5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa3 3eDIHu/zr1HMKErm+2SD6PO9umRef8V82o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCS KmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy 4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJC3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTT QbM0WUIBIcGmq38+OgUsMYu4NzLu7uZFAcmp6h8g Organization: Linaro In-Reply-To: <20250727193652.4029-2-krzysztof.kozlowski@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 27/07/2025 21:36, Krzysztof Kozlowski wrote: > Qualcomm DTS uses sorting of MMIO nodes by the unit address, so move > few nodes in SM8650 DTSI to fix that. > > Signed-off-by: Krzysztof Kozlowski > --- > arch/arm64/boot/dts/qcom/sm8650.dtsi | 414 +++++++++++++-------------- > 1 file changed, 207 insertions(+), 207 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi > index e14d3d778b71..2360d560dc86 100644 > --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi > @@ -3490,6 +3490,11 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, > }; > }; > > + rng: rng@10c3000 { > + compatible = "qcom,sm8650-trng", "qcom,trng"; > + reg = <0 0x010c3000 0 0x1000>; > + }; > + > cnoc_main: interconnect@1500000 { > compatible = "qcom,sm8650-cnoc-main"; > reg = <0 0x01500000 0 0x14080>; > @@ -3561,11 +3566,6 @@ mmss_noc: interconnect@1780000 { > #interconnect-cells = <2>; > }; > > - rng: rng@10c3000 { > - compatible = "qcom,sm8650-trng", "qcom,trng"; > - reg = <0 0x010c3000 0 0x1000>; > - }; > - > pcie0: pcie@1c00000 { > device_type = "pci"; > compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550"; > @@ -3926,38 +3926,6 @@ pcie1_phy: phy@1c0e000 { > status = "disabled"; > }; > > - cryptobam: dma-controller@1dc4000 { > - compatible = "qcom,bam-v1.7.0"; > - reg = <0 0x01dc4000 0 0x28000>; > - > - interrupts = ; > - > - #dma-cells = <1>; > - > - iommus = <&apps_smmu 0x480 0>, > - <&apps_smmu 0x481 0>; > - > - qcom,ee = <0>; > - qcom,num-ees = <4>; > - num-channels = <20>; > - qcom,controlled-remotely; > - }; > - > - crypto: crypto@1dfa000 { > - compatible = "qcom,sm8650-qce", "qcom,sm8150-qce", "qcom,qce"; > - reg = <0 0x01dfa000 0 0x6000>; > - > - interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS > - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; > - interconnect-names = "memory"; > - > - dmas = <&cryptobam 4>, <&cryptobam 5>; > - dma-names = "rx", "tx"; > - > - iommus = <&apps_smmu 0x480 0>, > - <&apps_smmu 0x481 0>; > - }; > - > ufs_mem_phy: phy@1d80000 { > compatible = "qcom,sm8650-qmp-ufs-phy"; > reg = <0 0x01d80000 0 0x2000>; > @@ -4079,6 +4047,38 @@ ice: crypto@1d88000 { > clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; > }; > > + cryptobam: dma-controller@1dc4000 { > + compatible = "qcom,bam-v1.7.0"; > + reg = <0 0x01dc4000 0 0x28000>; > + > + interrupts = ; > + > + #dma-cells = <1>; > + > + iommus = <&apps_smmu 0x480 0>, > + <&apps_smmu 0x481 0>; > + > + qcom,ee = <0>; > + qcom,num-ees = <4>; > + num-channels = <20>; > + qcom,controlled-remotely; > + }; > + > + crypto: crypto@1dfa000 { > + compatible = "qcom,sm8650-qce", "qcom,sm8150-qce", "qcom,qce"; > + reg = <0 0x01dfa000 0 0x6000>; > + > + interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "memory"; > + > + dmas = <&cryptobam 4>, <&cryptobam 5>; > + dma-names = "rx", "tx"; > + > + iommus = <&apps_smmu 0x480 0>, > + <&apps_smmu 0x481 0>; > + }; > + > tcsr_mutex: hwlock@1f40000 { > compatible = "qcom,tcsr-mutex"; > reg = <0 0x01f40000 0 0x20000>; > @@ -4962,6 +4962,176 @@ opp-202000000 { > }; > }; > > + usb_1_hsphy: phy@88e3000 { > + compatible = "qcom,sm8650-snps-eusb2-phy", > + "qcom,sm8550-snps-eusb2-phy"; > + reg = <0 0x088e3000 0 0x154>; > + > + clocks = <&tcsr TCSR_USB2_CLKREF_EN>; > + clock-names = "ref"; > + > + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; > + > + #phy-cells = <0>; > + > + status = "disabled"; > + }; > + > + usb_dp_qmpphy: phy@88e8000 { > + compatible = "qcom,sm8650-qmp-usb3-dp-phy"; > + reg = <0 0x088e8000 0 0x3000>; > + > + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, > + <&rpmhcc RPMH_CXO_CLK>, > + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, > + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; > + clock-names = "aux", > + "ref", > + "com_aux", > + "usb3_pipe"; > + > + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, > + <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; > + reset-names = "phy", > + "common"; > + > + power-domains = <&gcc USB3_PHY_GDSC>; > + > + #clock-cells = <1>; > + #phy-cells = <1>; > + > + orientation-switch; > + > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + > + usb_dp_qmpphy_out: endpoint { > + }; > + }; > + > + port@1 { > + reg = <1>; > + > + usb_dp_qmpphy_usb_ss_in: endpoint { > + remote-endpoint = <&usb_1_dwc3_ss>; > + }; > + }; > + > + port@2 { > + reg = <2>; > + > + usb_dp_qmpphy_dp_in: endpoint { > + remote-endpoint = <&mdss_dp0_out>; > + }; > + }; > + }; > + }; > + > + usb_1: usb@a6f8800 { > + compatible = "qcom,sm8650-dwc3", "qcom,dwc3"; > + reg = <0 0x0a6f8800 0 0x400>; > + > + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>, > + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>, > + <&pdc 14 IRQ_TYPE_EDGE_RISING>, > + <&pdc 15 IRQ_TYPE_EDGE_RISING>, > + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "pwr_event", > + "hs_phy_irq", > + "dp_hs_phy_irq", > + "dm_hs_phy_irq", > + "ss_phy_irq"; > + > + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, > + <&gcc GCC_USB30_PRIM_MASTER_CLK>, > + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, > + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, > + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, > + <&tcsr TCSR_USB3_CLKREF_EN>; > + clock-names = "cfg_noc", > + "core", > + "iface", > + "sleep", > + "mock_utmi", > + "xo"; > + > + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, > + <&gcc GCC_USB30_PRIM_MASTER_CLK>; > + assigned-clock-rates = <19200000>, <200000000>; > + > + resets = <&gcc GCC_USB30_PRIM_BCR>; > + > + interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY > + &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>; > + interconnect-names = "usb-ddr", > + "apps-usb"; > + > + power-domains = <&gcc USB30_PRIM_GDSC>; > + required-opps = <&rpmhpd_opp_nom>; > + > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + status = "disabled"; > + > + usb_1_dwc3: usb@a600000 { > + compatible = "snps,dwc3"; > + reg = <0 0x0a600000 0 0xcd00>; > + > + interrupts = ; > + > + iommus = <&apps_smmu 0x40 0>; > + > + phys = <&usb_1_hsphy>, > + <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; > + phy-names = "usb2-phy", > + "usb3-phy"; > + > + snps,hird-threshold = /bits/ 8 <0x0>; > + snps,usb2-gadget-lpm-disable; > + snps,dis_u2_susphy_quirk; > + snps,dis_enblslpm_quirk; > + snps,dis-u1-entry-quirk; > + snps,dis-u2-entry-quirk; > + snps,is-utmi-l1-suspend; > + snps,usb3_lpm_capable; > + snps,usb2-lpm-disable; > + snps,has-lpm-erratum; > + tx-fifo-resize; > + > + dma-coherent; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + > + usb_1_dwc3_hs: endpoint { > + }; > + }; > + > + port@1 { > + reg = <1>; > + > + usb_1_dwc3_ss: endpoint { > + remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; > + }; > + }; > + }; > + }; > + }; > + > iris: video-codec@aa00000 { > compatible = "qcom,sm8650-iris"; > reg = <0 0x0aa00000 0 0xf0000>; > @@ -5580,176 +5750,6 @@ dispcc: clock-controller@af00000 { > #power-domain-cells = <1>; > }; > > - usb_1_hsphy: phy@88e3000 { > - compatible = "qcom,sm8650-snps-eusb2-phy", > - "qcom,sm8550-snps-eusb2-phy"; > - reg = <0 0x088e3000 0 0x154>; > - > - clocks = <&tcsr TCSR_USB2_CLKREF_EN>; > - clock-names = "ref"; > - > - resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; > - > - #phy-cells = <0>; > - > - status = "disabled"; > - }; > - > - usb_dp_qmpphy: phy@88e8000 { > - compatible = "qcom,sm8650-qmp-usb3-dp-phy"; > - reg = <0 0x088e8000 0 0x3000>; > - > - clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, > - <&rpmhcc RPMH_CXO_CLK>, > - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, > - <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; > - clock-names = "aux", > - "ref", > - "com_aux", > - "usb3_pipe"; > - > - resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, > - <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; > - reset-names = "phy", > - "common"; > - > - power-domains = <&gcc USB3_PHY_GDSC>; > - > - #clock-cells = <1>; > - #phy-cells = <1>; > - > - orientation-switch; > - > - status = "disabled"; > - > - ports { > - #address-cells = <1>; > - #size-cells = <0>; > - > - port@0 { > - reg = <0>; > - > - usb_dp_qmpphy_out: endpoint { > - }; > - }; > - > - port@1 { > - reg = <1>; > - > - usb_dp_qmpphy_usb_ss_in: endpoint { > - remote-endpoint = <&usb_1_dwc3_ss>; > - }; > - }; > - > - port@2 { > - reg = <2>; > - > - usb_dp_qmpphy_dp_in: endpoint { > - remote-endpoint = <&mdss_dp0_out>; > - }; > - }; > - }; > - }; > - > - usb_1: usb@a6f8800 { > - compatible = "qcom,sm8650-dwc3", "qcom,dwc3"; > - reg = <0 0x0a6f8800 0 0x400>; > - > - interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>, > - <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>, > - <&pdc 14 IRQ_TYPE_EDGE_RISING>, > - <&pdc 15 IRQ_TYPE_EDGE_RISING>, > - <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; > - interrupt-names = "pwr_event", > - "hs_phy_irq", > - "dp_hs_phy_irq", > - "dm_hs_phy_irq", > - "ss_phy_irq"; > - > - clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, > - <&gcc GCC_USB30_PRIM_MASTER_CLK>, > - <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, > - <&gcc GCC_USB30_PRIM_SLEEP_CLK>, > - <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, > - <&tcsr TCSR_USB3_CLKREF_EN>; > - clock-names = "cfg_noc", > - "core", > - "iface", > - "sleep", > - "mock_utmi", > - "xo"; > - > - assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, > - <&gcc GCC_USB30_PRIM_MASTER_CLK>; > - assigned-clock-rates = <19200000>, <200000000>; > - > - resets = <&gcc GCC_USB30_PRIM_BCR>; > - > - interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS > - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, > - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY > - &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>; > - interconnect-names = "usb-ddr", > - "apps-usb"; > - > - power-domains = <&gcc USB30_PRIM_GDSC>; > - required-opps = <&rpmhpd_opp_nom>; > - > - #address-cells = <2>; > - #size-cells = <2>; > - ranges; > - > - status = "disabled"; > - > - usb_1_dwc3: usb@a600000 { > - compatible = "snps,dwc3"; > - reg = <0 0x0a600000 0 0xcd00>; > - > - interrupts = ; > - > - iommus = <&apps_smmu 0x40 0>; > - > - phys = <&usb_1_hsphy>, > - <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; > - phy-names = "usb2-phy", > - "usb3-phy"; > - > - snps,hird-threshold = /bits/ 8 <0x0>; > - snps,usb2-gadget-lpm-disable; > - snps,dis_u2_susphy_quirk; > - snps,dis_enblslpm_quirk; > - snps,dis-u1-entry-quirk; > - snps,dis-u2-entry-quirk; > - snps,is-utmi-l1-suspend; > - snps,usb3_lpm_capable; > - snps,usb2-lpm-disable; > - snps,has-lpm-erratum; > - tx-fifo-resize; > - > - dma-coherent; > - > - ports { > - #address-cells = <1>; > - #size-cells = <0>; > - > - port@0 { > - reg = <0>; > - > - usb_1_dwc3_hs: endpoint { > - }; > - }; > - > - port@1 { > - reg = <1>; > - > - usb_1_dwc3_ss: endpoint { > - remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; > - }; > - }; > - }; > - }; > - }; > - > pdc: interrupt-controller@b220000 { > compatible = "qcom,sm8650-pdc", "qcom,pdc"; > reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; Reviewed-by: Neil Armstrong