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Mon, 3 Aug 2026 04:51:26 +0000 (GMT) Message-ID: <3b524463-91de-4034-9478-7dbb5848262b@linux.ibm.com> Date: Mon, 3 Aug 2026 10:21:26 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 1/1] powerpc: enable dynamic preemption To: paulmck@kernel.org Cc: Jirka Hladky , "Christophe Leroy (CS GROUP)" , maddy@linux.ibm.com, linuxppc-dev@lists.ozlabs.org, mpe@ellerman.id.au, npiggin@gmail.com, bigeasy@linutronix.de, will@kernel.org, linux-kernel@vger.kernel.org References: <29a407ab-268e-4443-96dc-8f5f933cb63c@linux.ibm.com> <529b8d9f-54a0-4ec2-9886-83cd528e5e04@paulmck-laptop> <57d9de4a-65aa-44cf-9024-de4e5bdd1971@linux.ibm.com> <972db4f1-406b-477b-895e-59ffc643e384@kernel.org> <4be922b5-7dc2-48c1-938c-de02245bc5e2@linux.ibm.com> <1eab63fc-b70d-41ef-b720-8ae77d8e56d8@linux.ibm.com> Content-Language: en-US From: Shrikanth Hegde In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-Spam-Info: AW1haW4tMjYwODAzMDAzOSBTYWx0ZWRfX+3suSzZUhjLB TgHcfi5famx6Ihv6m2/GaUv77IOCmr8GFuPk/GsrU3lvL4Qv+JSwmu4hwXaXyc72v7xJfy5f9U+ 5yCfoQX1umBeTRDAYTXquZ4qwq7fkxc= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODAzMDAzOSBTYWx0ZWRfX0MwBNQQc/cV8 do0esE+MhYwtFN3Ip9U03vQESih+rw/qADtQDORdXK6UF92Ul3/Rzf8BIbQ1Xr6z7FKDE9Ibw+E 2e+J9bTFGh+NXCQUxAuZv2UDsOV2POwbrDlA7d9EaJaxt6PlL5vQn5fazq1YqPtsbM3ubKvEid6 Z33xn/6DcjW3tiA639A0laOX7YwqPH8+vIoRnaLIlvHfkyRmA4fr+ggb2CvzqC5OmkmD8W+kpX0 x2H+Ll5oqlmKhO8nB2qo0QJOO7WSm4xV/wP1XljAdNlkJI1ETr7mItqS+GA74s8IWxXC6A0M5nz awREmltxqgJpbGc+mrQoS84AQN4nGfhywX8lluismwQHV117N7Mv8a9R2snN4jGimBWQfU32/m3 UMC+woeVNyT604jt6/euFpf8AP3CRA9JsmCtwA967U7zpyy4G0Ar5E3qPJo6dFGdmdEIquQZdNx nfHH8pCe7NfU1DR8c9Q== X-Authority-Analysis: v=2.4 cv=SI1ykuvH c=1 sm=1 tr=0 ts=6a701e55 cx=c_pps a=bLidbwmWQ0KltjZqbj+ezA==:117 a=bLidbwmWQ0KltjZqbj+ezA==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=U7nrCbtTmkRpXpFmAIza:22 a=px_DR1VyBJH5svcGKecA:9 a=QEXdDO2ut3YA:10 X-Proofpoint-ORIG-GUID: 53ib-ODhAT5uWMKFuAar_-DXBhfJcX6M X-Proofpoint-GUID: 682vuke97HwPTVZmG_Tvj_qVAIfYnCim X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-02_06,2026-07-30_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 bulkscore=0 suspectscore=0 impostorscore=0 spamscore=0 phishscore=0 priorityscore=1501 lowpriorityscore=0 adultscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608030039 Hi Paul, >> I tried moving to PACA plus splitting 64 bit into need_resched and preempt >> count. But it doesn;t move the needle. But it maybe worth pursuing, >> since it could help preemption modes. It needs more work and needs numbers >> across benchmark. >> >>> Thanks for trying. Paul questioned whether barriers are actually >>> needed for preempt_count, or whether software interrupt disabling >>> would suffice (his words: "I can see why the preempt_count() >>> operations need to be interrupt-safe, but I don't see why you would >>> need barriers"). Any thoughts on whether that's feasible for >>> powerpc? >> >> Barrier are likely not the concern as it is mostly nop. >> Also, soft disabling interrupts needs to arch specific hooks to setup >> before preempt_disable and replay interrupts after preempt_enable. >> I don't think it would benefit since interrupt disabling during this likely >> shouldn't happen. Maybe I don't understand how that could work. > > For some reason, I remembered powerpc software-disabling interrupts, > but when I go look now, there is no such thing. Maybe powerpc used to > but no longer does. Or maybe I am just hallucinating. ;-) > > Thanx, Paul It is there still, static inline unsigned long arch_local_irq_save(void) { return irq_soft_mask_or_return(IRQS_DISABLED); } Sets the softmask bit, and any interrupt that arrives, gets added to a list and that will be replayed in arch_local_irq_restore. That will protect against the race of irq vs preempt count in __preempt_count_dec_and_test. In the PACA based PoC i have i tried to use it, but it doesn't make a difference, since this particular test accounts mainly preempt count overhead itself, which cannot be escaped in dynamic preemption. So, I think this is the tax we got to live with for dynamic preemption on RISC archs. But good thing is, its effect is limited to a very few microbenchmarks.