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Thu, 27 Oct 2022 05:40:55 -0700 (PDT) Received: from [10.27.10.248] ([195.165.23.90]) by smtp.gmail.com with ESMTPSA id a13-20020a2eb54d000000b0026de1bf528esm210847ljn.119.2022.10.27.05.40.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 27 Oct 2022 05:40:55 -0700 (PDT) Message-ID: <3b58b4a3-5e74-d848-211a-e127fb4440b6@linaro.org> Date: Thu, 27 Oct 2022 15:40:54 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.3.3 Subject: Re: [PATCH v1 5/5] clk: qcom: dispcc-sm8250: Disable link_div_clk_src for sm8150 Content-Language: en-GB To: Robert Foss , agross@kernel.org, bjorn.andersson@linaro.org, konrad.dybcio@somainline.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Bjorn Andersson , Jonathan Marek References: <20221027123432.1818530-1-robert.foss@linaro.org> <20221027123432.1818530-5-robert.foss@linaro.org> From: Dmitry Baryshkov In-Reply-To: <20221027123432.1818530-5-robert.foss@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 27/10/2022 15:34, Robert Foss wrote: > SM8150 does not have any of the link_div_clk_src clocks, so > let's disable them for this SoC. > > Signed-off-by: Robert Foss > --- > drivers/clk/qcom/dispcc-sm8250.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c > index d2aaa44ed3d4..f6f719616f63 100644 > --- a/drivers/clk/qcom/dispcc-sm8250.c > +++ b/drivers/clk/qcom/dispcc-sm8250.c > @@ -1289,6 +1289,10 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev) > disp_cc_pll1_config.config_ctl_hi1_val = 0x00000024; > disp_cc_pll1_config.user_ctl_hi1_val = 0x000000D0; > disp_cc_pll1_init.ops = &clk_alpha_pll_trion_ops; > + > + disp_cc_sm8250_clocks[DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC] = NULL; > + disp_cc_sm8250_clocks[DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] = NULL; > + disp_cc_sm8250_clocks[DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC] = NULL; We also have to fix link_intf clocks: disp_cc_mdss_dp_link_intf_clk.clkr.hw.init->parent_hws[0] = &disp_cc_mdss_dp_link_clk_src.clkr.hw; disp_cc_mdss_dp_link1_intf_clk.clkr.hw.init->parent_hws[0] = &disp_cc_mdss_dp_link1_clk_src.clkr.hw; disp_cc_mdss_edp_link_intf_clk.clkr.hw.init->parent_hws[0] = &disp_cc_mdss_edp_link_clk_src.clkr.hw; > } else if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8350-dispcc")) { > static struct clk_rcg2 * const rcgs[] = { > &disp_cc_mdss_byte0_clk_src, -- With best wishes Dmitry