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Thu, 15 Oct 2026 02:11:35 -0700 (PDT) X-Received: by 2002:a05:6a00:4099:b0:89e:37b1:b80d with SMTP id d2e1a72fcca58-89e37b1ba49mr2322643b3a.45.1792055494932; Thu, 15 Oct 2026 02:11:34 -0700 (PDT) Received: from [10.206.102.180] ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-89d804d1c10sm2087387b3a.35.2026.10.15.02.11.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 15 Oct 2026 02:11:33 -0700 (PDT) Message-ID: <3b58ccbe-bf6a-4b96-86c5-584d7feeeb6f@oss.qualcomm.com> Date: Thu, 15 Oct 2026 14:41:26 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/4] arm64: dts: qcom: nord: Add iris video node To: Shawn Guo , Vishnu Reddy Cc: Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Abel Vesa , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260919-nord-iris-v1-0-94428761ec06@oss.qualcomm.com> <20260919-nord-iris-v1-2-94428761ec06@oss.qualcomm.com> Content-Language: en-US From: Gourav Kumar In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=VKpIDNPX c=1 sm=1 tr=0 ts=6ad098c8 cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=y2grCCtr-R1DBeC8SxUA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDE1MDAzNiBTYWx0ZWRfXy49QEkJVRHTN fPpYl+RbBBqjbEm+/WeCtlQk/WpN/olRM6OweXMOGhxTFZU/sMcXMgwLhjn5V75dxqAYkqaPU47 AdeLQkSROVSWo0DvPa4Cfu3+exzj6Vg= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDE1MDAzNiBTYWx0ZWRfX9Oa1Nva0nPnR 9gYiRAAJBZrZxySyYGy9VpRC44jqKW7DIxOt3vyFrmRX2nXFBiMuIMpTyG0Tmj3Cm5AYsE1EpwO 7FQy0BEYzyW6OU6YY7b4L4zz+h88SmRFjFpd4gimd62Z/vXcgDj6CHnpXcqDHxTzX+SLcGuMV27 Lm7VguArG5q+dvkliNdIs1a3TyacTHiclq+t2p+Bv2CcpQ19TsQBbAonPR24yKWkdNQTKuHuO8n RaEUKsf3udG763RSWplBgXwCRObnfKGQ3vfHp7n5b8qR6sl0puOmXDbiOZRJ9ngKD7X2E7+A8Ie dnA1qbvssooCDl/bQWCMC88oiYX64V/3pHbXwHmfoebYWyG9kTB+YvjeCzBMQNvXr8LyAR+6Afj f+MxWBHb4WXA7PYlUWoiVDx4iE14/VtLmoI22rJz5sQvxa9qK45z3HYDiVMJ/Z/kGyWkIAoRVkb 488LY9y0KP50x0e0y0w== X-Proofpoint-ORIG-GUID: 1rOpgoiejSmjEHDC9KJvs9YGv8t14AgL X-Proofpoint-GUID: 1rOpgoiejSmjEHDC9KJvs9YGv8t14AgL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-13_01,2026-10-14_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 bulkscore=0 lowpriorityscore=0 impostorscore=0 suspectscore=0 malwarescore=0 phishscore=0 spamscore=0 clxscore=1015 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610150036 On 9/20/2026 6:46 PM, Shawn Guo wrote: > On Sat, Sep 19, 2026 at 10:14:56AM +0530, Vishnu Reddy wrote: >> Add iris video codec to nord SoC, which comes with significantly different >> powering up sequence than previous platforms, thus different clocks and >> resets. >> >> Signed-off-by: Vishnu Reddy >> --- >> arch/arm64/boot/dts/qcom/nord-embedded.dtsi | 114 ++++++++++++++++++++++++++++ >> 1 file changed, 114 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi >> index 74f4e6be8652..03f827f3e5fc 100644 >> --- a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi >> +++ b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi >> @@ -1428,6 +1428,120 @@ camcc: clock-controller@9ce0000 { >> #power-domain-cells = <1>; >> }; >> >> + iris: video-codec@aa00000 { >> + compatible = "qcom,nord-iris", "qcom,glymur-iris"; >> + reg = <0x0 0x0aa00000 0x0 0xf0000>; > > nord-embedded.dtsi is a place to accommodate Nord Embedded variant > specific resource descriptions, like clock, regulator, pinctrl, > interconnect, power domain, PHY, etc. The rest of descriptions should > go to nord.dtsi, like reg, interrupts, iommu, dma, etc. > Iris depends on providers such as videocc, nwgcc, hscnoc, and mc_virt, which are defined only in nord-embedded.dtsi. Moving the Iris node into nord.dtsi would leave unresolved references in DTS variants that don’t include the embedded file, causing DTB build failures. We should keep the iris node in nord-embedded.dtsi. Gourav Kumar > Shawn > >> + >> + clocks = <&nwgcc NW_GCC_VIDEO_AXI0_CLK>, >> + <&videocc VIDEO_CC_MVS0C_CLK>, >> + <&videocc VIDEO_CC_MVS0_CLK>, >> + <&nwgcc NW_GCC_VIDEO_AXI0C_CLK>, >> + <&videocc VIDEO_CC_MVS0C_FREERUN_CLK>, >> + <&videocc VIDEO_CC_MVS0_FREERUN_CLK>, >> + <&nwgcc NW_GCC_VIDEO_AXI1_CLK>, >> + <&videocc VIDEO_CC_MVS1_CLK>, >> + <&videocc VIDEO_CC_MVS1_FREERUN_CLK>; >> + clock-names = "core_iface", >> + "core", >> + "vcodec0_core", >> + "vcodec0_iface", >> + "core_freerun", >> + "vcodec0_core_freerun", >> + "vcodec1_iface", >> + "vcodec1_core", >> + "vcodec1_core_freerun"; >> + >> + dma-coherent; >> + >> + interconnects = <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY >> + &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, >> + <&mmss_noc MASTER_VIDEO_MVP0 QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "cpu-cfg", >> + "video-mem"; >> + >> + interrupts = ; >> + >> + memory-region = <&video_mem>; >> + >> + operating-points-v2 = <&iris_opp_table>; >> + >> + power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, >> + <&videocc VIDEO_CC_MVS0_GDSC>, >> + <&rpmhpd RPMHPD_MXC>, >> + <&rpmhpd RPMHPD_MMCX>, >> + <&videocc VIDEO_CC_MVS1_GDSC>; >> + power-domain-names = "venus", >> + "vcodec0", >> + "mxc", >> + "mmcx", >> + "vcodec1"; >> + >> + resets = <&nwgcc NW_GCC_VIDEO_AXI0_CLK_ARES>, >> + <&nwgcc NW_GCC_VIDEO_AXI0C_CLK_ARES>, >> + <&videocc VIDEO_CC_MVS0C_FREERUN_CLK_ARES>, >> + <&videocc VIDEO_CC_MVS0_FREERUN_CLK_ARES>, >> + <&nwgcc NW_GCC_VIDEO_AXI1_CLK_ARES>, >> + <&videocc VIDEO_CC_MVS1_FREERUN_CLK_ARES>; >> + reset-names = "core_bus", >> + "vcodec0_bus", >> + "core", >> + "vcodec0_core", >> + "vcodec1_bus", >> + "vcodec1_core"; >> + >> + #address-cells = <1>; >> + #size-cells = <1>; >> + dma-ranges = <0x0 0x0 0x0 0xffe00000>; >> + >> + status = "disabled"; >> + >> + non-pixel { >> + iommus = <&apps_smmu_1 0x0940 0x20>, >> + <&apps_smmu_1 0x0944 0x0>, >> + <&apps_smmu_1 0x0960 0x20>; >> + iommu-ranges = <0x25800000 0xda600000>; >> + }; >> + >> + pixel { >> + iommus = <&apps_smmu_1 0x0943 0x0>; >> + }; >> + >> + iris_opp_table: opp-table { >> + compatible = "operating-points-v2"; >> + >> + opp-240000000 { >> + opp-hz = /bits/ 64 <240000000 240000000 360000000>; >> + required-opps = <&rpmhpd_opp_svs>, >> + <&rpmhpd_opp_svs>; >> + }; >> + >> + opp-435000000 { >> + opp-hz = /bits/ 64 <435000000 435000000 652500000>; >> + required-opps = <&rpmhpd_opp_svs_l1>, >> + <&rpmhpd_opp_svs_l1>; >> + }; >> + >> + opp-480000000 { >> + opp-hz = /bits/ 64 <480000000 480000000 720000000>; >> + required-opps = <&rpmhpd_opp_svs_l1>, >> + <&rpmhpd_opp_nom>; >> + }; >> + >> + opp-533333333 { >> + opp-hz = /bits/ 64 <533333333 533333333 800000000>; >> + required-opps = <&rpmhpd_opp_svs_l1>, >> + <&rpmhpd_opp_turbo>; >> + }; >> + >> + opp-560000000 { >> + opp-hz = /bits/ 64 <560000000 560000000 840000000>; >> + required-opps = <&rpmhpd_opp_nom>, >> + <&rpmhpd_opp_turbo_l1>; >> + }; >> + }; >> + }; >> + >> videocc: clock-controller@aaf0000 { >> compatible = "qcom,nord-videocc"; >> reg = <0x0 0x0aaf0000 0x0 0x10000>; >> >> -- >> 2.34.1 >> >>