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client-ip=165.204.84.17; helo=satlexmb08.amd.com; pr=C Received: from satlexmb08.amd.com (165.204.84.17) by CH2PEPF0000014A.mail.protection.outlook.com (10.167.244.107) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9678.18 via Frontend Transport; Mon, 9 Mar 2026 02:58:25 +0000 Received: from satlexmb10.amd.com (10.181.42.219) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Sun, 8 Mar 2026 21:58:25 -0500 Received: from satlexmb08.amd.com (10.181.42.217) by satlexmb10.amd.com (10.181.42.219) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Sun, 8 Mar 2026 21:58:25 -0500 Received: from [172.31.177.127] (10.180.168.240) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server id 15.2.2562.17 via Frontend Transport; Sun, 8 Mar 2026 21:58:21 -0500 Message-ID: <3b6ff125-4110-4fbd-9da9-c510b3d43106@amd.com> Date: Mon, 9 Mar 2026 08:28:20 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 5/7] perf/amd/ibs: Enable RIP bit63 hardware filtering To: Ian Rogers CC: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Dapeng Mi , James Clark , Sadasivan Shaiju , , , , Manali Shukla , Santosh Shukla , Ananth Narayan , Sandipan Das , "Stephane Eranian" , Ravi Bangoria References: <20260216042530.1546-1-ravi.bangoria@amd.com> <20260216042530.1546-6-ravi.bangoria@amd.com> <8b99652d-155a-444e-8395-d461714bf4b8@amd.com> Content-Language: en-US From: Ravi Bangoria In-Reply-To: <8b99652d-155a-444e-8395-d461714bf4b8@amd.com> Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: /IghP9thR1gfjz9o9hY9zrTy0RdmfBaXpBumCFWYwZmwnBpQ+l857L3g+1I12+fayefEdOXnmnUSwS2gMb1dhKkS5AFVJZeiXhO9GudNCAAR03VcA3qeZx6sMppIPT9PREDUBuTJdLK4XbFU/7ohiIV5q94vV7i0M5TbKGGH4WMCmej1hWiaJeAIei0tvy9WBaJ0Kpt4GkuMgp3XOvXbEtCc/EIJEdj0w5abgzBNqwPLtWDvxJL6g2O0+hr4LvV4v1bgmyV5AT0wKk1zuOy9CkJ3NyqNgl/2LnFrCKufP5zAW2x8HO//pbR0Ifgj1w5TQRrpFZjhGbqjxCQqCTEFUwZcBU3YlJDwzFBO+FSZ91YzwmE6y6vePh95B8yvPLT9mVU5EdUUeaHLxTNKPcn8mXcPIwhawRxmFT5v86kt/qxYEQ7GLVL+l+/P5sLCKvm/ X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Mar 2026 02:58:25.8372 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 22193b55-c9fe-4985-9752-08de7d87bbda X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000014A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6590 Hi Ian, >> Does the bit 63 assumption hold for guest operating systems? > > Yes, this seems to be an issue, even with current swfilt approach. Let > me inspect the code and get back. All mainstream 64 bit OSes use the bit-63 set for kernel addresses and zero for userspace addresses. This norm does not apply to 32 bit guests, but those are rare, and profiling them with IBS would be even rarer. So, I'll document this limitation in the perf-amd-ibs man page. While looking at this, I found some issues in IBS. Below patch fixes it: --- >From deb6cdcbc60778b57a6eef60b2b7bd1b8e3cea74 Mon Sep 17 00:00:00 2001 From: Ravi Bangoria Date: Fri, 6 Mar 2026 04:52:00 +0000 Subject: [PATCH] perf/amd/ibs: Improve guest profiling IBS captures the RIP but not its privilege level. Since the NMI is delivered with delay, CPL can change between the IBS tag and NMI delivery. Add a check to catch and discard invalid guest samples using CPL stored in vCPU save area. This will work when there is user/kernel CPL change in between IBS tag and NMI delivery within the guest boundary. But it won't work when there is a guest entry or exit in between IBS tag and NMI delivery. When profiling a guest and the IBS RIP is valid, assign the sample IP from the IBS-captured RIP and set PERF_SAMPLE_IP in sample_flags so that perf_prepare_sample() do not overwrite the RIP with perf_guest_get_ip() from the vCPU save area. This keeps the perf sample IP consistent with IBS raw data, data_src, weight, phy_addr etc. The privilege level in the perf "misc" field can now go out of sync, as it is taken from the vCPU save area. Reported-by: Ian Rogers Closes: https://lore.kernel.org/r/CAP-5=fV_cJskvLRZhQQXMGAcPUb_Rg_b30PDJNXzxL49JK4B5g@mail.gmail.com Signed-off-by: Ravi Bangoria --- arch/x86/events/amd/ibs.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index eeb607b84dda..70408b0b1597 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -1415,6 +1415,7 @@ static int perf_ibs_handle_irq(struct perf_ibs *perf_ibs, struct pt_regs *iregs) unsigned int msr; u64 *buf, *config, period, new_config = 0; int br_target_idx = -1; + unsigned int guest_state; if (!test_bit(IBS_STARTED, pcpu->state)) { fail: @@ -1526,6 +1527,42 @@ static int perf_ibs_handle_irq(struct perf_ibs *perf_ibs, struct pt_regs *iregs) regs.flags |= PERF_EFLAGS_EXACT; } + guest_state = perf_guest_state(); + if (!event->attr.exclude_guest && guest_state & PERF_GUEST_ACTIVE) { + /* + * IBS captures the RIP but not its privilege level. Since + * NMI arrives delayed, CPL might change in between IBS tag + * and the NMI delivery. Below checks can identify and filter + * out invalid samples when the CPL changes are within the + * guest boundary. However, these checks fail to handle cases + * where the CPU performs a guest entry or exit in between + * the IBS tag and the NMI delivery. + */ + if (event->attr.exclude_kernel && !(guest_state & PERF_GUEST_USER)) { + throttle = perf_event_account_interrupt(event); + goto out; + } + if (event->attr.exclude_user && guest_state & PERF_GUEST_USER) { + throttle = perf_event_account_interrupt(event); + goto out; + } + + /* + * Assign the IBS RIP value directly in the perf sample here + * to prevent perf_prepare_sample() from retrieving it from + * the vCPU save-area. With this, rest of the perf sample + * fields (raw data, data_src, weight, phy_addr, etc.) will + * remain in sync with sample IP. However, privilege level + * captured as part of perf sample "misc" field could now + * go out of sync since privilege level is fetched from the + * vCPU save area. + */ + if (regs.flags & PERF_EFLAGS_EXACT) { + data.ip = regs.ip; + data.sample_flags |= PERF_SAMPLE_IP; + } + } + if (((ibs_caps & IBS_CAPS_BIT63_FILTER) || (event->attr.config2 & IBS_SW_FILTER_MASK)) && perf_ibs_discard_sample(perf_ibs, event, ®s, &ibs_data, br_target_idx)) { -- 2.43.0