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AJvYcCUOYMAF9mSbbzpSzjiPMIczxKkNPms3so5pv8vv446dcXqG537I3uXhxZhsEovwPOsO9eO86VX5/+I8v14JDlQdOgZekK/HwHNC+O6O X-Gm-Message-State: AOJu0Ywr3UxgotOctKRUdx8iPf5uyPhCenn1P/cM05y4CvMHubzukF7x dMH32epZy4+Ov5J7XlNw7acTfG9xLze5CO198+nXtL7jZ1VaGoY1KWfRiYje+Gw= X-Google-Smtp-Source: AGHT+IEWHh0Ctaa5g16fNMt4g7gBrPzAyrnWxhO+d4dNl2ZiaY9Bn69hrV+muBoeAYW8Wrtjx8jTNw== X-Received: by 2002:a2e:95d9:0:b0:2d7:21f:90ef with SMTP id y25-20020a2e95d9000000b002d7021f90efmr1699128ljh.1.1711625154661; Thu, 28 Mar 2024 04:25:54 -0700 (PDT) Received: from draszik.lan ([80.111.64.44]) by smtp.gmail.com with ESMTPSA id fb7-20020a05600c520700b00414969894a1sm3877017wmb.13.2024.03.28.04.25.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Mar 2024 04:25:54 -0700 (PDT) Message-ID: <3b9d28405f01c7bc23075492dbb501ebde0edbfa.camel@linaro.org> Subject: Re: [PATCH v2 3/3] clk: samsung: gs101: propagate PERIC0 USI SPI clock rate From: =?ISO-8859-1?Q?Andr=E9?= Draszik To: Tudor Ambarus , peter.griffin@linaro.org, krzysztof.kozlowski@linaro.org Cc: alim.akhtar@samsung.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, willmcvicker@google.com, kernel-team@android.com, s.nawrocki@samsung.com, cw00.choi@samsung.com, mturquette@baylibre.com, sboyd@kernel.org, semen.protsenko@linaro.org, linux-clk@vger.kernel.org, jaewon02.kim@samsung.com Date: Thu, 28 Mar 2024 11:25:53 +0000 In-Reply-To: <20240326172813.801470-4-tudor.ambarus@linaro.org> References: <20240326172813.801470-1-tudor.ambarus@linaro.org> <20240326172813.801470-4-tudor.ambarus@linaro.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.50.2-1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Tue, 2024-03-26 at 17:28 +0000, Tudor Ambarus wrote: > When SPI transfer is being prepared, the spi-s3c64xx driver will call > clk_set_rate() to change the rate of SPI source clock (IPCLK). But IPCLK > is a gate (leaf) clock, so it must propagate the rate change up the > clock tree, so that corresponding MUX/DIV clocks can actually change > their values. Add CLK_SET_RATE_PARENT flag to corresponding clocks for > all USI instances in GS101 PERIC0: USI{1-8, 14}. This change involves the > following clocks: >=20 > PERIC0 USI*: >=20 > =C2=A0=C2=A0=C2=A0 Clock=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 Div range=C2=A0=C2=A0= =C2=A0 MUX Selection > =C2=A0=C2=A0=C2=A0 ------------------------------------------------------= ------------- > =C2=A0=C2=A0=C2=A0 gout_peric0_peric0_top0_ipclk_*=C2=A0=C2=A0=C2=A0 -=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - > =C2=A0=C2=A0=C2=A0 dout_peric0_usi*_usi=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /1..16=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 - > =C2=A0=C2=A0=C2=A0 mout_peric0_usi*_usi_user=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0 -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 {24.5 MHz, 400 MHz} >=20 > With input clock of 400 MHz this scheme provides the following IPCLK > rate range, for each USI block: >=20 > =C2=A0=C2=A0=C2=A0 PERIC0 USI*:=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 1.5 M= Hz ... 400 MHz >=20 > Accounting for internal /4 divider in SPI blocks, and because the max > SPI frequency is limited at 50 MHz, it gives us next SPI SCK rates: >=20 > =C2=A0=C2=A0=C2=A0 PERIC0 USI_SPI*:=C2=A0=C2=A0 384 KHz ... 49.9 MHz >=20 > Which shall be fine for the applications of the SPI bus. >=20 > Note that with this we allow the reparenting of the MUX_USIx clocks to > OSCCLK. Each instance of the USI IP has its own MUX_USI clock, thus the > reparenting of a MUX_USI clock corresponds to a single instance of the > USI IP. The datasheet mentions OSCCLK just in the low-power mode > context, but the downstream driver reparents too the MUX_USI clocks to > OSCCLK. Follow the downstream driver and do the same. >=20 > Fixes: 893f133a040b ("clk: samsung: gs101: add support for cmu_peric0") > Signed-off-by: Tudor Ambarus Acked-by: Andr=C3=A9 Draszik