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Thu, 5 Nov 2026 19:27:00 -0600 From: Melody Wang To: CC: LKML , Tom Lendacky , , Melody Wang Subject: [PATCH v6 6/7] x86/sev: Allow the guest to configure interrupt vectors for the hypervisor Date: Fri, 6 Nov 2026 01:25:32 +0000 Message-ID: <3bb412990005d4ec37e0e5d89a3524ea5e9d5117.1793926736.git.huibo.wang@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF000793FE:EE_|DS5PPFF8845FFFB:EE_ X-MS-Office365-Filtering-Correlation-Id: 86cbecac-443a-4cd1-e1df-08df3ba50f9b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|36860700016|1800799024|23010399003|22082099003|18002099003|3023799007|10067099003|56012099006|11063799006|261026140227099003|261102123227099003|261028144727099003|261022105027099003|261026121527099003|261009223027099003|261021121427099003|261022075727099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: ZB45V6FO5Zm1F7X7AZvn++ZBTeM5wxRAc5ut2/i4nyOmWCCJWm5Oj7FmA8C15+3+9sAx2Q6i7QDgoN/pxocwRd6t90docnTSOMDHzuk/LaQSN+BWPz85RPkXodWI+hqEKzwcnl0SHkx7EYku7eLuQyMcRWmzC8B1RNCt6dSNul8bKsx5+MlX4Vhx4MZ8sKQ61dsnLDy8nRfT8AeyzqZaqjqein2SaPhWJ3y7uEbdp9Uq+NTvpPT8zU1unWeEnV5ivRGXdOgbPJhDjMikQcl7apW4NvF0X4lGfA1k1ux+XEOxS9eYs+FtYcpONUQvMpI4D8SpKwGVsS+NQsnq+XO19U9Q3tn+it3viL0fnW/ERhWRLDGlHWeJiWYovr3Be4+1NcflQZa4WpVIppktdjXcgtxtrFJka+oFuREvkhZRmU1srPKOqxRsy9BHkFi2caBG X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Nov 2026 01:27:02.6978 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 86cbecac-443a-4cd1-e1df-08df3ba50f9b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF000793FE.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS5PPFF8845FFFB The SVSM APIC protocol supports 5 API calls. SVSM_APIC_CONFIGURE_VECTOR (shortened to SVSM_APIC_CONFIG_VECTOR for brevity), call 4, provides for the guest to configure an interrupt vector which the guest allows and the hypervisor can use to signal interrupts for it. Implement this call, and make the default interrupt setting permissive when detecting an SVSM. Signed-off-by: Melody Wang --- arch/x86/boot/startup/sev-startup.c | 20 ++++++++++++++++++++ arch/x86/boot/startup/sme.c | 3 +++ arch/x86/include/asm/sev.h | 9 +++++++++ 3 files changed, 32 insertions(+) diff --git a/arch/x86/boot/startup/sev-startup.c b/arch/x86/boot/startup/sev-startup.c index 789e99d38d17..bf11e5420dd2 100644 --- a/arch/x86/boot/startup/sev-startup.c +++ b/arch/x86/boot/startup/sev-startup.c @@ -191,6 +191,26 @@ static void __init svsm_setup(struct cc_blob_sev_info *cc_info) boot_svsm_caa_pa = pa; } +/* + * Configure all interrupts as permissive by default for Alternate Injection + * enabled SNP guest. + */ +void __init svsm_config_alt_inj_vectors(void) +{ + struct svsm_call call = {}; + int ret; + + if (sev_status & MSR_AMD64_SNP_ALTERNATE_INJ) { + call.caa = rip_rel_ptr(&boot_svsm_ca_page); + call.rax = SVSM_APIC_CALL(SVSM_APIC_CONFIG_VECTOR); + call.rcx = SVSM_IRQ_ENABLE_ALL << 8; + + ret = svsm_call_msr_protocol(&call); + if (ret) + sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_ALT_INJ_FAIL); + } +} + bool __init snp_init(struct boot_params *bp) { struct cc_blob_sev_info *cc_info; diff --git a/arch/x86/boot/startup/sme.c b/arch/x86/boot/startup/sme.c index c07a2c381ed1..3f92db52c557 100644 --- a/arch/x86/boot/startup/sme.c +++ b/arch/x86/boot/startup/sme.c @@ -566,6 +566,9 @@ void __init sme_enable(struct boot_params *bp) physical_mask &= ~me_mask; cc_vendor = CC_VENDOR_AMD; cc_set_mask(me_mask); + + if (snp_vmpl) + svsm_config_alt_inj_vectors(); } #ifdef CONFIG_MITIGATION_PAGE_TABLE_ISOLATION diff --git a/arch/x86/include/asm/sev.h b/arch/x86/include/asm/sev.h index d916a5dcd6af..dec4c6b217f0 100644 --- a/arch/x86/include/asm/sev.h +++ b/arch/x86/include/asm/sev.h @@ -34,6 +34,13 @@ enum es_result { ES_RETRY, /* Retry instruction emulation */ }; +enum svsm_vec_enable { + SVSM_IRQ_DISABLE_SINGLE, + SVSM_IRQ_ENABLE_SINGLE, + SVSM_IRQ_DISABLE_ALL, + SVSM_IRQ_ENABLE_ALL, +}; + struct es_fault_info { unsigned long vector; unsigned long error_code; @@ -518,6 +525,7 @@ void snp_set_memory_shared(unsigned long vaddr, unsigned long npages); void snp_set_memory_private(unsigned long vaddr, unsigned long npages); void snp_set_wakeup_secondary_cpu(void); bool snp_init(struct boot_params *bp); +void svsm_config_alt_inj_vectors(void); void snp_dmi_setup(void); int snp_issue_svsm_attest_req(u64 call_id, struct svsm_call *call, struct svsm_attest_call *input); void snp_accept_memory(phys_addr_t start, phys_addr_t end); @@ -626,6 +634,7 @@ static inline void snp_set_memory_shared(unsigned long vaddr, unsigned long npag static inline void snp_set_memory_private(unsigned long vaddr, unsigned long npages) { } static inline void snp_set_wakeup_secondary_cpu(void) { } static inline bool snp_init(struct boot_params *bp) { return false; } +static inline void svsm_config_alt_inj_vectors(void) { } static inline void snp_dmi_setup(void) { } static inline int snp_issue_svsm_attest_req(u64 call_id, struct svsm_call *call, struct svsm_attest_call *input) { -- 2.43.0