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From: Marek Szyprowski <m.szyprowski@samsung.com>
To: "André Draszik" <andre.draszik@linaro.org>,
	"Vinod Koul" <vkoul@kernel.org>,
	"Kishon Vijay Abraham I" <kishon@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Sylwester Nawrocki" <s.nawrocki@samsung.com>,
	"Alim Akhtar" <alim.akhtar@samsung.com>
Cc: Peter Griffin <peter.griffin@linaro.org>,
	Tudor Ambarus <tudor.ambarus@linaro.org>,
	Sam Protsenko <semen.protsenko@linaro.org>,
	Will McVicker <willmcvicker@google.com>,
	Roy Luo <royluo@google.com>,
	kernel-team@android.com, linux-phy@lists.infradead.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-samsung-soc@vger.kernel.org
Subject: Re: [PATCH v4 6/7] phy: exynos5-usbdrd: subscribe to orientation notifier if required
Date: Fri, 14 Feb 2025 20:30:19 +0100	[thread overview]
Message-ID: <3c0b77e6-357d-453e-8b63-4757c3231bde@samsung.com> (raw)
In-Reply-To: <20241206-gs101-phy-lanes-orientation-phy-v4-6-f5961268b149@linaro.org>

On 06.12.2024 17:31, André Draszik wrote:
> gs101's SS phy needs to be configured differently based on the
> connector orientation, as the SS link can only be established if the
> mux is configured correctly.
>
> The code to handle programming of the mux is in place already, this commit
> now adds the missing pieces to subscribe to the Type-C orientation
> switch event.
>
> Note that for this all to work we rely on the USB controller
> re-initialising us. It should invoke our .exit() upon cable unplug, and
> during cable plug we'll receive the orientation event after which we
> expect our .init() to be called.
>
> Above reinitialisation happens if the DWC3 controller can enter runtime
> suspend automatically. For the DWC3 driver, this is an opt-in:
>      echo auto > /sys/devices/.../11110000.usb/power/control
> Once done, things work as long as the UDC is not bound as otherwise it
> stays busy because it doesn't cancel / stop outstanding TRBs. For now
> we have to manually unbind the UDC in that case:
>       echo "" > sys/kernel/config/usb_gadget/.../UDC
>
> Note that if the orientation-switch property is missing from the DT,
> the code will behave as before this commit (meaning for gs101 it will
> work in SS mode in one orientation only). Other platforms are not
> affected either way.
>
> Signed-off-by: André Draszik <andre.draszik@linaro.org>
>
> ---
> v3:
> * drop init to -1 of phy_drd->orientation (Vinod)
> * avoid #ifdef and switch to normal conditional IS_ENABLED() for
>    CONFIG_TYPEC
>
> v2:
> * move #include typec_mux.h from parent patch into this one (Peter)
> ---
>   drivers/phy/samsung/Kconfig              |  1 +
>   drivers/phy/samsung/phy-exynos5-usbdrd.c | 56 ++++++++++++++++++++++++++++++++
>   2 files changed, 57 insertions(+)
>
> diff --git a/drivers/phy/samsung/Kconfig b/drivers/phy/samsung/Kconfig
> index f10afa3d7ff5..fc7bd1088576 100644
> --- a/drivers/phy/samsung/Kconfig
> +++ b/drivers/phy/samsung/Kconfig
> @@ -80,6 +80,7 @@ config PHY_EXYNOS5_USBDRD
>   	tristate "Exynos5 SoC series USB DRD PHY driver"
>   	depends on (ARCH_EXYNOS && OF) || COMPILE_TEST
>   	depends on HAS_IOMEM
> +	depends on TYPEC || (TYPEC=n && COMPILE_TEST)
>   	depends on USB_DWC3_EXYNOS
>   	select GENERIC_PHY
>   	select MFD_SYSCON

I've just noticed that the above disables Exynos DRD PHY driver in the 
default exynos_defconfig for arm 32bit. Enabling CONFIG_TYPEC is 
exynos_defconfig probably is the easiest way to fix this. I will send a 
patch then.

> diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c
> index 61e0de4b3d4b..8fc15847cfd8 100644
> --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c
> +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c
> @@ -24,6 +24,7 @@
>   #include <linux/regulator/consumer.h>
>   #include <linux/soc/samsung/exynos-regs-pmu.h>
>   #include <linux/usb/typec.h>
> +#include <linux/usb/typec_mux.h>
>   
>   /* Exynos USB PHY registers */
>   #define EXYNOS5_FSEL_9MHZ6		0x0
> @@ -394,6 +395,7 @@ struct exynos5_usbdrd_phy_drvdata {
>    * @extrefclk: frequency select settings when using 'separate
>    *	       reference clocks' for SS and HS operations
>    * @regulators: regulators for phy
> + * @sw: TypeC orientation switch handle
>    * @orientation: TypeC connector orientation - normal or flipped
>    */
>   struct exynos5_usbdrd_phy {
> @@ -415,6 +417,7 @@ struct exynos5_usbdrd_phy {
>   	u32 extrefclk;
>   	struct regulator_bulk_data *regulators;
>   
> +	struct typec_switch_dev *sw;
>   	enum typec_orientation orientation;
>   };
>   
> @@ -1397,6 +1400,55 @@ static int exynos5_usbdrd_phy_clk_handle(struct exynos5_usbdrd_phy *phy_drd)
>   	return 0;
>   }
>   
> +static int exynos5_usbdrd_orien_sw_set(struct typec_switch_dev *sw,
> +				       enum typec_orientation orientation)
> +{
> +	struct exynos5_usbdrd_phy *phy_drd = typec_switch_get_drvdata(sw);
> +
> +	scoped_guard(mutex, &phy_drd->phy_mutex)
> +		phy_drd->orientation = orientation;
> +
> +	return 0;
> +}
> +
> +static void exynos5_usbdrd_orien_switch_unregister(void *data)
> +{
> +	struct exynos5_usbdrd_phy *phy_drd = data;
> +
> +	typec_switch_unregister(phy_drd->sw);
> +}
> +
> +static int exynos5_usbdrd_setup_notifiers(struct exynos5_usbdrd_phy *phy_drd)
> +{
> +	int ret;
> +
> +	if (!IS_ENABLED(CONFIG_TYPEC))
> +		return 0;
> +
> +	if (device_property_present(phy_drd->dev, "orientation-switch")) {
> +		struct typec_switch_desc sw_desc = { };
> +
> +		sw_desc.drvdata = phy_drd;
> +		sw_desc.fwnode = dev_fwnode(phy_drd->dev);
> +		sw_desc.set = exynos5_usbdrd_orien_sw_set;
> +
> +		phy_drd->sw = typec_switch_register(phy_drd->dev, &sw_desc);
> +		if (IS_ERR(phy_drd->sw))
> +			return dev_err_probe(phy_drd->dev,
> +					     PTR_ERR(phy_drd->sw),
> +					     "Failed to register TypeC orientation switch\n");
> +
> +		ret = devm_add_action_or_reset(phy_drd->dev,
> +					       exynos5_usbdrd_orien_switch_unregister,
> +					       phy_drd);
> +		if (ret)
> +			return dev_err_probe(phy_drd->dev, ret,
> +					     "Failed to register TypeC orientation devm action\n");
> +	}
> +
> +	return 0;
> +}
> +
>   static const struct exynos5_usbdrd_phy_config phy_cfg_exynos5[] = {
>   	{
>   		.id		= EXYNOS5_DRDPHY_UTMI,
> @@ -1786,6 +1838,10 @@ static int exynos5_usbdrd_phy_probe(struct platform_device *pdev)
>   	if (ret)
>   		return dev_err_probe(dev, ret, "failed to get regulators\n");
>   
> +	ret = exynos5_usbdrd_setup_notifiers(phy_drd);
> +	if (ret)
> +		return ret;
> +
>   	dev_vdbg(dev, "Creating usbdrd_phy phy\n");
>   
>   	for (i = 0; i < EXYNOS5_DRDPHYS_NUM; i++) {
>
Best regards
-- 
Marek Szyprowski, PhD
Samsung R&D Institute Poland


  parent reply	other threads:[~2025-02-14 19:30 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-12-06 16:31 [PATCH v4 0/7] USB31DRD phy updates for Google Tensor gs101 (orientation & DWC3 rpm) André Draszik
2024-12-06 16:31 ` [PATCH v4 1/7] dt-bindings: phy: samsung,usb3-drd-phy: add blank lines between DT properties André Draszik
2024-12-06 16:31 ` [PATCH v4 2/7] dt-bindings: phy: samsung,usb3-drd-phy: gs101: require Type-C properties André Draszik
2024-12-11 15:47   ` Rob Herring (Arm)
2024-12-06 16:31 ` [PATCH v4 3/7] phy: exynos5-usbdrd: convert to dev_err_probe André Draszik
2024-12-26 17:29   ` William McVicker
2024-12-06 16:31 ` [PATCH v4 4/7] phy: exynos5-usbdrd: fix EDS distribution tuning (gs101) André Draszik
2024-12-26 17:31   ` William McVicker
2024-12-06 16:31 ` [PATCH v4 5/7] phy: exynos5-usbdrd: gs101: configure SS lanes based on orientation André Draszik
2024-12-26 17:31   ` William McVicker
2024-12-06 16:31 ` [PATCH v4 6/7] phy: exynos5-usbdrd: subscribe to orientation notifier if required André Draszik
2024-12-07 21:31   ` Peter Griffin
2024-12-11 17:55     ` Peter Griffin
2024-12-26 17:33   ` William McVicker
2025-02-14 19:30   ` Marek Szyprowski [this message]
2025-02-15  9:24     ` Krzysztof Kozlowski
2025-02-15  9:34       ` Krzysztof Kozlowski
2025-02-15 10:07     ` Krzysztof Kozlowski
2025-02-15 16:09       ` André Draszik
2024-12-06 16:31 ` [PATCH v4 7/7] phy: exynos5-usbdrd: allow DWC3 runtime suspend with UDC bound (E850+) André Draszik
2024-12-07 22:03   ` Peter Griffin
2024-12-11 17:53     ` Peter Griffin
2024-12-26 17:34   ` William McVicker
2024-12-26 17:28 ` [PATCH v4 0/7] USB31DRD phy updates for Google Tensor gs101 (orientation & DWC3 rpm) William McVicker
2025-01-06 14:26 ` André Draszik
2025-02-13  6:59   ` André Draszik
2025-02-13 18:16 ` Vinod Koul

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