Re: [PATCH net-next v2 2/4] dt-bindings: net: dsa: Add SoC-e SWIP switch

[Vasilij Strassheim <v.strassheim@linutronix.de>]

On Thu, 2026-09-10 at 14:12 +0200, Andrew Lunn wrote:
> > > Since this is an FPGA, i assume there are no internal PHYs. Mixed mode
> > > is not something FPGAs do. There are sometime "interesting"
> > > relationships between port number and address on the MDIO bus. But
> > > without internal PHYs you don't need to worry about this.
> > > 
> > 
> > Correct, the FPGA IP has no internal PHYs. Each port is associated with
> > a dedicated external MDIO bus.
> 
> How is a port and the MDIO bus associated?

I had to clarify a few details.
In the particular bitstream and board design I am using, MDIO is enabled
for every external switch port. Each external port therefore has its own
MDIO interface. This is what I meant by "associated". However, it's a
property of this FPGA configuration, not a general Linux requirement or
an inherent mapping for every instance of the IP core.

> 
> Linux, in general, does not care. You have a collection of MDIO
> busses, and on those busses you have a collection of PHYs. The MACs
> use a phandle, or some other means to point to the PHY it should use.
> 
> Given this is a 31 port switch, why would you dedicate 62 pins to
> MDIO, two per port, when you can put 32 PHYs on one MDIO bus?
> 
> So i doubt there is a strong association between port and MDIO bus.
> 
> What i could image is the one real MDIO bus controller is in global
> scope within the RTL design. And then the logic to provide a port with
> its multiplexor on that shared bus is in the per port RTL design
> scope. I've not done much FPGA design, but i assume if you don't
> connect the per port MDIO lines to anything, while place and route is
> performed, they get optimised out?


Yes, MDIO can be enabled per port when generating the bitstream. If it
is disabled for a port, the corresponding physical interface is not
generated, so your assumption about unused interfaces being omitted is
correct.
Linux will still model the topology in the usual way: the generated
interfaces are exposed as MDIO buses, and each switch port refers to its
PHY through a phy-handle. The bus selector identifies a generated MDIO
interface and should not generally be interpreted as a switch port
number.

> 
> > > So in theory, a 0 port switch is possible!
> > 
> > In theory, yes, but I prefer to treat it as invalid until it can be
> > tested.
> 
> Yes, i would treat 0, 1 and probably 2 as invalid. 2 ports would
> technically work in the DSA setup, but is pretty much pointless. It
> only gets interesting with 3 ports or more.

I will add an additional check and reject configurations with fewer than
3 ports.

> 
>      Andrew

Thanks,
Vasilij