From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-m1973186.qiye.163.com (mail-m1973186.qiye.163.com [220.197.31.86]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8F98049550C for ; Thu, 23 Jul 2026 12:25:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.86 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784809543; cv=none; b=H9ONyK46d3nyqDKMBLhauYJYFCPn41HcMPoepITUoa9k5lZ32knRCZltgC1MB+l1BTCt30n1cdNfIUlsHrUwvJAtn+ZplCs7XCuO20uQ1vjWbfaul/RTsRsrGycMfvGbg4vLZt9hhz3vNeoKy6p3JN17SX34WM4TUKxDoAalqPk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784809543; c=relaxed/simple; bh=SY/O29yTON4YSvpnBrseEIkVDUYR3aYqfQ18JHh9+7g=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=WxRJS7ed6VQ3sG2T4u/DPvDSesg+VMib8kffRUZc6i9rUJXoRKJ28gdSMecHfNh+zzozm7dLKPtVrqs1roxwHDbEaaGuC/vo0XxddDQvOUcf53sS6ir2hSa+YteJLQc4iVSPCfjbGeOOWx2Cz3qtWAtMoXN4VcoN9JeGoG3y6ko= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=ILO0ZOy6; arc=none smtp.client-ip=220.197.31.86 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="ILO0ZOy6" Received: from [172.16.12.77] (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 475247b54; Thu, 23 Jul 2026 19:50:02 +0800 (GMT+08:00) Message-ID: <3c35b6cc-2664-46fe-b3d9-d7a8edb0d4da@rock-chips.com> Date: Thu, 23 Jul 2026 19:50:02 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 3/8] phy: rockchip: samsung-hdptx: Fix rate recalculation for 3.2GHz FRL To: Cristian Ciocaltea , Vinod Koul , Neil Armstrong , Heiko Stuebner , Algea Cao , Dmitry Baryshkov Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Sashiko References: <20260612-hdptx-clk-fixes-v4-0-ce5e1d456cda@collabora.com> <20260612-hdptx-clk-fixes-v4-3-ce5e1d456cda@collabora.com> Content-Language: en-US From: Andy Yan In-Reply-To: <20260612-hdptx-clk-fixes-v4-3-ce5e1d456cda@collabora.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-HM-Tid: 0a9f8ecfac7a09d8kunm031a521c55c8 X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1kYFggdWUFKV1ktWUFJV1kPCRoVCBIfWUFZQ09PGVYfTx9DQ01IQ0 4aTB1WFRQJFhoXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0 tIVUpLSEpKQkxVSktLVUpCS0tZBg++ DKIM-Signature: a=rsa-sha256; b=ILO0ZOy6jaDMFagrc9EJexKlpfA6zSgcenDe7NVMxXO7quzqdap7HNR72aJVydfGrGDy1mlP6b7vGM4VX7VctsCnLwLJYXXEjZ4QX6ltKRMYgOIrWgjLSqS96iuZIqNdIo9L60ipYdOzDhqLODDMe2dE9h4Dtq7+S4SzDEOGTA8=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=+UZ5aO1jJH6/Bdo7Zxa7na+WVnOeBPu1jv/v7v1eFhw=; h=date:mime-version:subject:message-id:from; Hello, On 6/12/26 07:45, Cristian Ciocaltea wrote: > rk_hdptx_phy_clk_calc_rate_from_pll_cfg() is currently unable to handle > cascade mode for the 3.2GHz FRL operating mode, as it relies solely on > LCPLL_LCVCO_MODE_EN_MASK to determinate the rate from the > rk_hdptx_frl_lcpll_cfg array. Since there is no entry for this > particular rate, the function returns 0. > > This is the only rate which requires LC_REF_CLK_SEL to be set in > GRF_HDPTX_CON0, hence extend the FRL matching accordingly. > > Reported-by: Sashiko > Closes: https://sashiko.dev/#/patchset/20260611-hdptx-clk-fixes-v3-0-67b1b0c00e16@collabora.com?part=1 > Fixes: de5dba833118 ("phy: rockchip: samsung-hdptx: Add HDMI 2.1 FRL support") > Signed-off-by: Cristian Ciocaltea Reviewed-by: Andy Yan > --- > drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 33 ++++++++++++++++------- > 1 file changed, 24 insertions(+), 9 deletions(-) > > diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c > index 8c044381b83a..b210c1a88b25 100644 > --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c > +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c > @@ -2206,16 +2206,31 @@ static u64 rk_hdptx_phy_clk_calc_rate_from_pll_cfg(struct rk_hdptx_phy *hdptx) > return 0; > lcpll_hw.sdc_n = (val & LCPLL_SDC_N_MASK) >> 1; > > - for (i = 0; i < ARRAY_SIZE(rk_hdptx_frl_lcpll_cfg); i++) { > - const struct lcpll_config *cfg = &rk_hdptx_frl_lcpll_cfg[i]; > + ret = regmap_read(hdptx->grf, GRF_HDPTX_CON0, &val); > + if (ret) > + return 0; > > - if (cfg->pms_mdiv == lcpll_hw.pms_mdiv && > - cfg->pms_sdiv == lcpll_hw.pms_sdiv && > - cfg->sdm_num_sign == lcpll_hw.sdm_num_sign && > - cfg->sdm_num == lcpll_hw.sdm_num && > - cfg->sdm_deno == lcpll_hw.sdm_deno && > - cfg->sdc_n == lcpll_hw.sdc_n) > - return cfg->rate; > + if (val & LC_REF_CLK_SEL) { > + if (lcpll_hw.pms_mdiv == 0x6b && > + lcpll_hw.sdm_num_sign == 0x01 && > + lcpll_hw.sdm_num == 0x02 && > + lcpll_hw.sdm_deno == 0x09 && > + lcpll_hw.sdc_n == FIELD_GET(LCPLL_SDC_N_MASK, 0x02)) > + return FRL_8G4L_RATE; > + } else { > + const struct lcpll_config *cfg; > + > + for (i = 0; i < ARRAY_SIZE(rk_hdptx_frl_lcpll_cfg); i++) { > + cfg = &rk_hdptx_frl_lcpll_cfg[i]; > + > + if (cfg->pms_mdiv == lcpll_hw.pms_mdiv && > + cfg->pms_sdiv == lcpll_hw.pms_sdiv && > + cfg->sdm_num_sign == lcpll_hw.sdm_num_sign && > + cfg->sdm_num == lcpll_hw.sdm_num && > + cfg->sdm_deno == lcpll_hw.sdm_deno && > + cfg->sdc_n == lcpll_hw.sdc_n) > + return cfg->rate; > + } > } > > dev_dbg(hdptx->dev, "%s no FRL match found\n", __func__); >