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Sat, 14 Mar 2026 03:31:41 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ThreadId: ABMmOHXEXk43 Date: Sat, 14 Mar 2026 08:31:20 +0100 From: "Arnd Bergmann" To: "Krzysztof Kozlowski" , "Ghennadi Procopciuc" , "Khristine Andreea Barbulescu" Cc: "Linus Walleij" , "Bartosz Golaszewski" , "Krzysztof Kozlowski" , "Conor Dooley" , "Chester Lin" , "Matthias Brugger" , "Ghennadi Procopciuc" , "Larisa Grigore" , "Lee Jones" , "Shawn Guo" , "Sascha Hauer" , "Fabio Estevam" , "Aisheng Dong" , "Jacky Bai" , "Greg Kroah-Hartman" , "Rafael J . Wysocki" , "Alberto Ruiz" , "Christophe Lizzi" , devicetree@vger.kernel.org, "Enric Balletbo" , "Eric Chanudet" , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, "open list:GPIO SUBSYSTEM" , linux-kernel@vger.kernel.org, "NXP S32 Linux Team" , "Pengutronix Kernel Team" , "Vincent Guittot" , "Rob Herring" Message-Id: <3c454da1-d949-4258-87ce-8b545000bf01@app.fastmail.com> In-Reply-To: References: <20260120115923.3463866-1-khristineandreea.barbulescu@oss.nxp.com> <20260120115923.3463866-2-khristineandreea.barbulescu@oss.nxp.com> <20260121021913.GA1704619-robh@kernel.org> <7d200097-51bc-4404-be8b-f536d0ecfc25@oss.nxp.com> <21531cdd-5ab9-493e-a722-61b98117e2c4@kernel.org> <22a5a072-847e-4cfd-8abd-e37163f73265@oss.nxp.com> Subject: Re: [PATCH v8 01/10] dt-bindings: mfd: add support for the NXP SIUL2 module Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable On Fri, Mar 13, 2026, at 18:10, Krzysztof Kozlowski wrote: > On 25/02/2026 10:40, Ghennadi Procopciuc wrote: >> On 2/23/2026 3:14 PM, Krzysztof Kozlowski wrote: >>>> there are no resources allocated specifically for nodes like >>>> "nxp,s32g-siul2-syscfg". Their consumers are the pinctrl/gpio >>>> driver and other drivers that read SoC=E2=80=91specific information= from >>>> those shared registers. >>>> =20 >>>> My alternative is to keep two separate syscon providers for the >>> >>> You got review already. >>> >> I still believe that nvmem is a suitable and accurate mechanism for >> describing SoC=E2=80=91specific identification information, as origin= ally >> proposed in [0], assuming the necessary adjustments are made. >>=20 >> More specifically, instead of modeling software-defined cells, the nv= mem >> layout would describe the actual hardware registers backing this >> information. One advantage of this approach is that consumer nodes (f= or >> example PCIe, Ethernet, or other IPs that need SoC identification dat= a) >> can reference these registers using the standard nvmem-cells / >> nvmem-cell-names mechanism, without introducing custom, per-subsystem >> bindings. > > nvmem is applicable only if this is NVMEM. Information about the soc is > not NVMEM, unless this are blow out fuses / efuse. Does not look like, > because SoC information is set probably during design phase, not board > assembly. Agreed, nvmem clearly makes no sense here, the patch description appears to accurately describe the MMIO area as hardware registers with a fixed meaning rather than a convention for how the memory is being used. That said, there is probably room for improvement, since some of the register contents are read-only and could just be accessed by the boot firmware in order to move the information into more regular DT properties instead of defining bindings for drivers to access the information in raw form. Arnd