Re: [PATCH v7 22/31] irqchip/gic-v5: Add GICv5 LPI/IPI support

[Jinjie Ruan <ruanjinjie@huawei.com>]

On 2025/8/8 16:19, Lorenzo Pieralisi wrote:
> On Fri, Aug 08, 2025 at 09:20:30AM +0800, Jinjie Ruan wrote:
>>
>>

[...]

>>
>> I also did not see any place in the code where these pointers are
>> accessed, nor did I see in section "L2_ISTE, Level 2 interrupt state
>> table entry" that L2_ISTE can be accessed by software. So, are these
>> states of the LPI interrupt maintained by the GIC hardware itself?
> 
> The IST table is where interrupt state and configuration is kept -
> it is managed by GIC IRS HW. SW controls interrupt configuration
> through GIC instructions.
> 
> It is therefore a false positive, I will send the patch below for
> inclusion.

Thank you for your explanation, I now have a general understanding of
how IST works.

> 
> Thanks,
> Lorenzo
> 
>>>
>>> -- >8 --
>>> diff --git a/drivers/irqchip/irq-gic-v5-irs.c b/drivers/irqchip/irq-gic-v5-irs.c
>>> index ad1435a858a4..e8a576f66366 100644
>>> --- a/drivers/irqchip/irq-gic-v5-irs.c
>>> +++ b/drivers/irqchip/irq-gic-v5-irs.c
>>> @@ -5,6 +5,7 @@
>>>  
>>>  #define pr_fmt(fmt)	"GICv5 IRS: " fmt
>>>  
>>> +#include <linux/kmemleak.h>
>>>  #include <linux/log2.h>
>>>  #include <linux/of.h>
>>>  #include <linux/of_address.h>
>>> @@ -117,6 +118,7 @@ static int __init gicv5_irs_init_ist_linear(struct gicv5_irs_chip_data *irs_data
>>>  		kfree(ist);
>>>  		return ret;
>>>  	}
>>> +	kmemleak_ignore(ist);
>>>  
>>>  	return 0;
>>>  }
>>> @@ -232,6 +234,7 @@ int gicv5_irs_iste_alloc(const u32 lpi)
>>>  		kfree(l2ist);
>>>  		return ret;
>>>  	}
>>> +	kmemleak_ignore(l2ist);
>>>  
>>>  	/*
>>>  	 * Make sure we invalidate the cache line pulled before the IRS
>>>
>