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Subject: Re: [PATCH 11/16] x86/asm/64: Use a percpu trampoline stack for IDT
 entries
To: Andy Lutomirski <luto@kernel.org>, X86 ML <x86@kernel.org>
References: <cover.1511195781.git.luto@kernel.org>
 <3ff604702987cf6af1e191705fd937517ceeeeb7.1511195781.git.luto@kernel.org>
Cc: Borislav Petkov <bpetkov@suse.de>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Brian Gerst <brgerst@gmail.com>,
        Linus Torvalds <torvalds@linux-foundation.org>,
        Josh Poimboeuf <jpoimboe@redhat.com>
From: Dave Hansen <dave.hansen@intel.com>
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Date: Tue, 21 Nov 2017 10:57:31 -0800
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On 11/20/2017 09:07 AM, Andy Lutomirski wrote:
> --- a/arch/x86/entry/entry_64.S
> +++ b/arch/x86/entry/entry_64.S
> @@ -560,6 +560,14 @@ END(irq_entries_start)
>  	.macro interrupt func
>  	cld
>  	ALLOC_PT_GPREGS_ON_STACK
> +
> +	testb	$3, CS(%rsp)
> +	jz	1f
> +	SWAPGS
> +	call	switch_to_thread_stack
> +	SWAPGS
> +1:

This looks really weird to me.  SWAPGS, switch stack, and SWAPGS again?

Is this so that we can use some per-cpu data in switch_to_thread_stack,
and then put GS back so that the normal, non-trampoline entry code can
do its normal SWAPGS voodoo?