From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mta0.migadu.com (out-184.mta0.migadu.com [91.218.175.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 82FE93E1736 for ; Wed, 16 Sep 2026 06:07:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.184 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789538869; cv=none; b=nw0EQqlht0VblGVIZmglDlqTqF7DVJAzYhf0PFpXHoezQQfajyret6qOwdLnyuZEz/sR/JYyccDFn6EYv5uhcj8J3mNgrPWx2hW+R8XbWOFqCJJXLJZ/FTqnpxT/O0iGvOd6JNTPHJBOWSL07dUlo+08+RPN+HmARi/OZ43R5g8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789538869; c=relaxed/simple; bh=Upb7fT52apWjvHoBWvo7REZj2hvpKQlKFSELhYivXVA=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=LAJ1dWxIarYoPyV8Up9LUXdmKy6Dujfu213jH5CObRzrMD8qhu7FUl0n96ZIul9IyjkH9jBkv0GT9dZMGpx2JLYhtVELxFDTlGpCT5qlN1+Odu+fOMBqrH30GIuLL++Brj5rRjTh/hKx4y9HpoXfz6w4BDacHN+mhPCfjjOu7IY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=Y2+B9Kxl; arc=none smtp.client-ip=91.218.175.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="Y2+B9Kxl" X-Envelope-To: linux-kernel@vger.kernel.org DKIM-Signature: a=rsa-sha256; bh=Upb7fT52apWjvHoBWvo7REZj2hvpKQlKFSELhYivXVA=; c=simple/simple; d=linux.dev; h=from:to:subject:date:message-id:mime-version:content-type; s=key1; t=1789538865; v=1; x=1790143665; b=Y2+B9KxlkH+zmzRYIEye9AQ9nX6ij9HMIb+/pS6h7nVpKJ/GeWv5xagxg2TgDTvnZCxYVdby y1PBiEjl29ipzXORwXkxyV1sH18mt5KqmRwO3uJJHNL4Fh5fHWLJ2KrnhPqowUuJ+uLCdkcbKPD LLE1tPV5mpbwhjqKGyxJAGcM= X-Envelope-To: linux-kernel@vger.kernel.org Received: by mta12.migadu.com with ESMTPS id 6188b57fbf076545; Wed, 16 Sep 2026 06:07:45 +0000 X-Mizu-Trace-ID: 6188b57fbf076545 X-Migadu-Flow: FLOW_OUT Date: Wed, 16 Sep 2026 09:07:36 +0300 From: Matti Vaittinen To: Matti Vaittinen , Matti Vaittinen , Matti Vaittinen Cc: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liam Girdwood , Mark Brown , Matti Vaittinen , Stephen Boyd , Brian Masney , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Alexandre Belloni , Michael Walle , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org, Sverdlin@mva-rohm, Alexander Subject: [PATCH v4 02/10] dt-bindings: rohm,bd*: Ref common ROHM bindings Message-ID: <3cf6bb01a3a129f2b0b1d6418049dbdb1711873a.1789538455.git.mazziesaccount@gmail.com> Reply-To: Matti Vaittinen References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="malQGX+h/gVqItxd" Content-Disposition: inline In-Reply-To: --malQGX+h/gVqItxd Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable =46rom: Matti Vaittinen The commonly used ROHM PMIC bindings were added into rohm,pmic-pins.yaml. Keeping commonly used properties in one file can ease both the maintaining the bindings and the reviewing process. Reference the common bindings from rohm,pmic-pins.yaml, instead of declaring them from the scratch for every PMIC using them. Keep the PMIC variant specific information (like supported pin functions) in PMIC the specific files, so unsupported values won't be allowed. Signed-off-by: Matti Vaittinen Reviewed-by: Rob Herring (Arm) Reviewed-by: Linus Walleij --- Revision history: v3 =3D> : - No changes v2: - New patch --- .../bindings/mfd/rohm,bd71815-pmic.yaml | 9 +++--- .../bindings/mfd/rohm,bd71828-pmic.yaml | 9 +++--- .../bindings/mfd/rohm,bd72720-pmic.yaml | 29 +++---------------- 3 files changed, 12 insertions(+), 35 deletions(-) diff --git a/Documentation/devicetree/bindings/mfd/rohm,bd71815-pmic.yaml b= /Documentation/devicetree/bindings/mfd/rohm,bd71815-pmic.yaml index 4fc78efaa550..0a67de054674 100644 --- a/Documentation/devicetree/bindings/mfd/rohm,bd71815-pmic.yaml +++ b/Documentation/devicetree/bindings/mfd/rohm,bd71815-pmic.yaml @@ -15,6 +15,9 @@ description: | for LED and a 500 mA single-cell linear charger. Also included is a Coul= omb counter, a real-time clock (RTC), and a 32.768 kHz clock gate and two GP= Os. =20 +allOf: + - $ref: rohm,pmic-pins.yaml# + properties: compatible: const: rohm,bd71815 @@ -44,11 +47,7 @@ properties: clock-output-names: const: bd71815-32k-out =20 - rohm,clkout-open-drain: - description: clk32kout mode. Set to 1 for "open-drain" or 0 for "cmos". - $ref: /schemas/types.yaml#/definitions/uint32 - minimum: 0 - maximum: 1 + rohm,clkout-open-drain: true =20 rohm,charger-sense-resistor-micro-ohms: minimum: 10000 diff --git a/Documentation/devicetree/bindings/mfd/rohm,bd71828-pmic.yaml b= /Documentation/devicetree/bindings/mfd/rohm,bd71828-pmic.yaml index 09e7d68e92bf..e5043dec990d 100644 --- a/Documentation/devicetree/bindings/mfd/rohm,bd71828-pmic.yaml +++ b/Documentation/devicetree/bindings/mfd/rohm,bd71828-pmic.yaml @@ -15,6 +15,9 @@ description: | single-cell linear charger. Also included is a Coulomb counter, a real-t= ime clock (RTC), and a 32.768 kHz clock gate. =20 +allOf: + - $ref: rohm,pmic-pins.yaml# + properties: compatible: oneOf: @@ -49,11 +52,7 @@ properties: clock-output-names: const: bd71828-32k-out =20 - rohm,clkout-open-drain: - description: clk32kout mode. Set to 1 for "open-drain" or 0 for "cmos". - $ref: /schemas/types.yaml#/definitions/uint32 - minimum: 0 - maximum: 1 + rohm,clkout-open-drain: true =20 rohm,charger-sense-resistor-micro-ohms: minimum: 10000 diff --git a/Documentation/devicetree/bindings/mfd/rohm,bd72720-pmic.yaml b= /Documentation/devicetree/bindings/mfd/rohm,bd72720-pmic.yaml index b094542339e8..52d0f6e4ef0f 100644 --- a/Documentation/devicetree/bindings/mfd/rohm,bd72720-pmic.yaml +++ b/Documentation/devicetree/bindings/mfd/rohm,bd72720-pmic.yaml @@ -15,6 +15,9 @@ description: and a 3000 mA switching charger. ICs also include a Coulomb counter, a real-time clock (RTC), GPIOs and a 32.768 kHz clock gate. =20 +allOf: + - $ref: rohm,pmic-pins.yaml# + # In addition to the properties found from the charger node, PMICs # use properties from a static battery node. Please see the: # Documentation/devicetree/bindings/power/supply/battery.yaml @@ -80,10 +83,7 @@ properties: clock-output-names: const: bd71828-32k-out =20 - rohm,clkout-open-drain: - description: clk32kout mode. Set to 1 for "open-drain" or 0 for "cmos". - $ref: /schemas/types.yaml#/definitions/uint32 - maximum: 1 + rohm,clkout-open-drain: true =20 rohm,charger-sense-resistor-micro-ohms: minimum: 10000 @@ -103,14 +103,6 @@ properties: $ref: /schemas/leds/rohm,bd71828-leds.yaml =20 rohm,pin-fault_b: - $ref: /schemas/types.yaml#/definitions/string - description: - PMIC has an OTP option to use fault_b-pin for different - purposes. Set this property accordingly. OTP options are - OTP0 - bi-directional FAULT_B or READY indicator depending on a - 'sub option' - OTP1 - GPO - OTP2 - Power sequencer output. enum: - faultb - readyind @@ -119,14 +111,6 @@ properties: =20 patternProperties: "^rohm,pin-dvs[0-1]$": - $ref: /schemas/types.yaml#/definitions/string - description: - PMIC has 4 different OTP options to determine the use of dvs-pins. - OTP0 - regulator RUN state control. - OTP1 - GPI. - OTP2 - GPO. - OTP3 - Power sequencer output. - This property specifies the use of the pin. enum: - dvs-input - gpi @@ -134,11 +118,6 @@ patternProperties: - pwrseq =20 "^rohm,pin-exten[0-1]$": - $ref: /schemas/types.yaml#/definitions/string - description: PMIC has an OTP option to use exten0-pin for different - purposes. Set this property accordingly. - OTP0 - GPO - OTP1 - Power sequencer output. enum: - gpo - pwrseq --=20 2.55.0 --malQGX+h/gVqItxd Content-Type: application/pgp-signature; name=signature.asc -----BEGIN PGP SIGNATURE----- iQEzBAEBCgAdFiEEIx+f8wZb28fLKEhTeFA3/03aocUFAmqqMigACgkQeFA3/03a ocUXYAgAhEaj8NCKJON+bDhs7SLujY4Xr5unO/R2V7msAYOwEOyXjmInpIXi6yul PUlUAI6wxSqyBObmkKsjHZx6BcIJndr74mFEmSY81P8dMcZXApk22ix7mzTf1BNT Ze+2CMOvMRLLExvJRCfQv71GtmRIG3+Wgbe7SOy3ME+fdVz0K4xBSN9QPNDXxzs2 zcpo1XwqdIp+/t9iuwJt7FcCFoFijMilDHBogFf1S5Ph3bcJdUy/Ql4700o7MVaa evUQmzJgh7twd0mdrNJn0Gy0ROO1Q3F3rbV+27wUKcZYUQrEFJMLsNtv6+bgHHz9 AXVjJL3b9HBOSlz5Yjz1PgkPfHmWFQ== =u1UN -----END PGP SIGNATURE----- --malQGX+h/gVqItxd--