Re: [PATCH 2/3] dt-bindings: arm: cpus: Add edac-enabled property

[Vijay Balakrishna <vijayb@linux.microsoft.com>]

On 5/20/2025 5:07 PM, Rob Herring wrote:
> On Mon, May 19, 2025 at 4:03 AM Borislav Petkov <bp@alien8.de> wrote:
>>
>> On Thu, May 15, 2025 at 05:06:12PM -0700, Vijay Balakrishna wrote:
>>> From: Sascha Hauer <s.hauer@pengutronix.de>
>>>
>>> Some ARM Cortex CPUs including A72 have Error Detection And
>>> Correction (EDAC) support on their L1 and L2 caches. This is implemented
>>> in implementation defined registers, so usage of this functionality is
>>> not safe in virtualized environments or when EL3 already uses these
>>> registers. This patch adds a edac-enabled flag which can be explicitly
>>> set when EDAC can be used.
>>>
>>> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
>>> [vijayb: Limit A72 in the commit message]
>>> Signed-off-by: Vijay Balakrishna <vijayb@linux.microsoft.com>
>>> ---
>>>   Documentation/devicetree/bindings/arm/cpus.yaml | 6 ++++++
>>>   1 file changed, 6 insertions(+)
>>
>> This needs an Ack from DT maintainers.
> 
> That will happen when my review comments are implemented. Those were
> on v1. Not this v1, but the prior v1. Version your patches correctly
> please.

Sorry, I will include in my next patch series.

Vijay