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[212.182.62.129]) by smtp.gmail.com with ESMTPSA id 36-20020a9f22a7000000b007ce1febd008sm1658773uan.34.2024.01.23.10.20.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 23 Jan 2024 10:20:43 -0800 (PST) Message-ID: <3d029d7c-7efb-42bb-a16d-30cf965f410b@linaro.org> Date: Tue, 23 Jan 2024 19:20:38 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 07/11] arm64: dts: qcom: x1e80100: Add PCIe nodes Content-Language: en-US To: Abel Vesa , Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sibi Sankar , Rajendra Nayak Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20240123-x1e80100-dts-missing-nodes-v4-0-072dc2f5c153@linaro.org> <20240123-x1e80100-dts-missing-nodes-v4-7-072dc2f5c153@linaro.org> From: Konrad Dybcio In-Reply-To: <20240123-x1e80100-dts-missing-nodes-v4-7-072dc2f5c153@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 1/23/24 12:01, Abel Vesa wrote: > Add nodes for PCIe 4 and 6 controllers and their PHYs for X1E80100 platform. > > Co-developed-by: Sibi Sankar > Signed-off-by: Sibi Sankar > Co-developed-by: Rajendra Nayak > Signed-off-by: Rajendra Nayak > Signed-off-by: Abel Vesa > --- [...] > + > + interrupts = ; > + interrupt-names = "msi"; You may want to add ITS MSIs too [...] > + > + resets = <&gcc GCC_PCIE_6A_BCR>, > + <&gcc GCC_PCIE_6A_LINK_DOWN_BCR>; The second entry is misaligned Konrad