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Mon, 06 Jul 2026 23:51:58 -0700 (PDT) X-Received: by 2002:a17:90b:45:b0:384:229e:1d1c with SMTP id 98e67ed59e1d1-38757b81a3amr3675113a91.31.1783406719846; Mon, 06 Jul 2026 23:45:19 -0700 (PDT) Received: from [10.217.198.242] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-387d20a32e3sm542564a91.14.2026.07.06.23.45.15 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 06 Jul 2026 23:45:19 -0700 (PDT) Message-ID: <3d12c33e-6aae-4396-bcee-f4159a741cc0@oss.qualcomm.com> Date: Tue, 7 Jul 2026 12:15:14 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: "Maulik Shah (mkshah)" Subject: Re: [PATCH v3 8/8] arm64: dts: qcom: x1e80100: Add deepest idle state To: Konrad Dybcio , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Gleixner , Linus Walleij , Sneh Mankad Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, Sneh Mankad References: <20260616-hamoa_pdc_v3-v3-0-4d8e1504ea75@oss.qualcomm.com> <20260616-hamoa_pdc_v3-v3-8-4d8e1504ea75@oss.qualcomm.com> Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: 3r_YONZcAIWXURTAQmgNTPTtl2QrkHeN X-Authority-Analysis: v=2.4 cv=HstG3UTS c=1 sm=1 tr=0 ts=6a4ca20f cx=c_pps a=JIY1xp/sjQ9K5JH4t62bdg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=hcMOYrp8kfDHR0m5M2YA:9 a=QEXdDO2ut3YA:10 a=tNoRWFLymzeba-QzToBc:22 X-Proofpoint-ORIG-GUID: 3r_YONZcAIWXURTAQmgNTPTtl2QrkHeN X-Proofpoint-Spam-Info: AW1haW4tMjYwNzA3MDA2NCBTYWx0ZWRfXxDGeg7wSNilS wRyo7Krq2dLBiipoxoKr12mS/+3Y8Nj3a7oR1MLfCP/fyzfoU4MH/zBInlz0gZJJOxXSVS+ljes jSRJOr/G+39AkvIdqgYIEwam+EZA7Ao= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzA3MDA2NCBTYWx0ZWRfX8yeSUlKnzGj8 Lmw6nLtO4VEA9jvYurck4tXIXeq4GQQ6OYuQWgKxKsQmKeLkpyu0ysBJWI2w4ANPVD1wWQlPYQl ybcmECi542syDLV/ewZiWfxTtdHGxx1KFP2YByh3vB1uJQtr0/XrIHkRyP8EPywd1pyxOcv7ceN KaXFQzBn+kW9u0HMpniOogmewnqeoKYyGE8JNbqQ6/d339CSYR1kyMSxWNbP4KcLKkVCNJKSnBP wfNH9/WHzRMjsp1exzcxrESS3T2M6ZK/N7Np+FHFNvNZskRmrbmRpScoOIchUrUQt5HWdZDVVek kJ7AVhWlZQTdM0Oh4xmU/7aqCVkljXMu7JgBK6ohEgBrMCx70VgmG2fqDbzpBttyq2TKvk4VwAb tEt6ShWNk7KIHkBrEeS68E2XKX9EWyxYqn02Lc2Jcb82ecn70f4V8oI++8Ql0Vyi+15lNcGuNHK x0jKViBThMiIN2BAazw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-07_01,2026-07-06_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 impostorscore=0 suspectscore=0 malwarescore=0 bulkscore=0 clxscore=1015 spamscore=0 adultscore=0 lowpriorityscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607070064 On 6/18/2026 1:55 PM, Konrad Dybcio wrote: > On 6/16/26 11:25 AM, Maulik Shah wrote: >> Add deepest idle state as GPIO IRQs can work as wakeup capable interrupts >> in deepest idle state. >> >> Signed-off-by: Maulik Shah >> --- >> arch/arm64/boot/dts/qcom/hamoa.dtsi | 10 +++++++++- >> 1 file changed, 9 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi >> index 4ba751a65142..47e425003028 100644 >> --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi >> +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi >> @@ -302,6 +302,14 @@ cluster_cl5: cluster-sleep-1 { >> exit-latency-us = <4000>; >> min-residency-us = <7000>; >> }; >> + >> + domain_ss3: domain-sleep-0 { >> + compatible = "domain-idle-state"; >> + arm,psci-suspend-param = <0x0200c354>; >> + entry-latency-us = <2800>; >> + exit-latency-us = <4400>; > > The DSDT has "wake_latency" (presumably the same as exit latency) set > to 5000 us, should we follow? DSDT wake_latency seems to be entry+exit latency. Will follow DSDT in v4. This requires update in CL5 latency too, for now will follow 2500+2500 split, which is closing matching with actual entry/exit latency too. > > FWIW, the 2800/4400 numbers here are the exact same as for sm8650.. > which doesn't sound very reassuring> > >> + min-residency-us = <9000>; > > This number matches the DSDT > > Should the entry latency then be 9000 - 5000 = 4000? CPU idle states with arm,idle-states compatible allows "wakeup-latency-us", which should match DSDT given "wake_latency". Using this will avoid such confusion in future and will plan to use this but in a separate series. This needs some more changes for Cluster idle states with domain-idle-state compatible. (cluster states do not support the "wakeup-latency-us" and still needs entry/exit-latency-us) Sneh is already working on this and will soon send out a series. Thanks, Maulik > > > On a separate note, the DSDT also defines: > > SS1 (0x02000154, total=7500, exit=500) > SS2 (0x02000254, total=8000, exit=3000) > > These are obviously shallower states, but perhaps they could still > be useful? > So far SS1/SS2 not proven to be helping much on power/performance for Linux. Thanks, Maulik