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b=kgotgtLlkItS6SsCvZL2VsZslNoSKjI4Lmd84VLHjnC5GJdbvFgJHly+NO3tQtcW3mWTibVwUbaJysnQDQHRXR+xvP3THqv6abra8Us+BDp1S70llP3LtBUx9TD+NpyjVojlSRBVDEUg57+ScSqjlWoF6GwNr8p/7h6nflX/Y3M= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amd.com; Received: from MW3PR12MB4553.namprd12.prod.outlook.com (2603:10b6:303:2c::19) by IA1PR12MB6209.namprd12.prod.outlook.com (2603:10b6:208:3e7::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8158.27; Sat, 23 Nov 2024 00:09:45 +0000 Received: from MW3PR12MB4553.namprd12.prod.outlook.com ([fe80::b0ef:2936:fec1:3a87]) by MW3PR12MB4553.namprd12.prod.outlook.com ([fe80::b0ef:2936:fec1:3a87%4]) with mapi id 15.20.8158.024; Sat, 23 Nov 2024 00:09:45 +0000 Message-ID: <3d162f99-2fa8-4034-80a9-ea7ea43fda0b@amd.com> Date: Fri, 22 Nov 2024 18:09:40 -0600 User-Agent: Mozilla Thunderbird Reply-To: babu.moger@amd.com Subject: Re: [PATCH v9 18/26] x86/resctrl: Add the interface to assign/update counter assignment To: Reinette Chatre , babu.moger@amd.com, corbet@lwn.net, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com Cc: fenghua.yu@intel.com, x86@kernel.org, hpa@zytor.com, thuth@redhat.com, paulmck@kernel.org, rostedt@goodmis.org, akpm@linux-foundation.org, xiongwei.song@windriver.com, pawan.kumar.gupta@linux.intel.com, daniel.sneddon@linux.intel.com, perry.yuan@amd.com, sandipan.das@amd.com, kai.huang@intel.com, xiaoyao.li@intel.com, seanjc@google.com, jithu.joseph@intel.com, brijesh.singh@amd.com, xin3.li@intel.com, ebiggers@google.com, andrew.cooper3@citrix.com, mario.limonciello@amd.com, james.morse@arm.com, tan.shaopeng@fujitsu.com, tony.luck@intel.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, peternewman@google.com, maciej.wieczor-retman@intel.com, eranian@google.com, jpoimboe@kernel.org, thomas.lendacky@amd.com References: <3851fbd6ccd1cdc504229e4c7f7d2575c13f5bd6.1730244116.git.babu.moger@amd.com> <1757cedb-e5b8-45fa-9b70-4c78b5770624@intel.com> <77f808e3-1dea-4a85-b574-dcdcb03697f9@amd.com> <7fe1298c-d026-460e-aa0d-76144abce524@intel.com> <2e774d31-d63c-4bc8-b88a-1cee74533a5d@amd.com> Content-Language: en-US From: "Moger, Babu" In-Reply-To: Content-Type: text/plain; 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The global assignment is tracked >>>>>> using the mbm_cntr_free_map field in the struct resctrl_mon, while >>>>>> domain-specific assignments are tracked using the mbm_cntr_map field >>>>>> in the struct rdt_mon_domain. Allocation begins at the global level >>>>>> and is then applied individually to each domain. >>>>>> >>>>>> Introduce an interface to allocate these counters and update the >>>>>> corresponding domains accordingly. >>>>>> >>>>>> Signed-off-by: Babu Moger >>>>>> --- >>>>> >>>>> ... >>>>> >>>>>> diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/resctrl/internal.h >>>>>> index 00f7bf60e16a..cb496bd97007 100644 >>>>>> --- a/arch/x86/kernel/cpu/resctrl/internal.h >>>>>> +++ b/arch/x86/kernel/cpu/resctrl/internal.h >>>>>> @@ -717,6 +717,8 @@ unsigned int mon_event_config_index_get(u32 evtid); >>>>>>   int resctrl_arch_config_cntr(struct rdt_resource *r, struct rdt_mon_domain *d, >>>>>>                    enum resctrl_event_id evtid, u32 rmid, u32 closid, >>>>>>                    u32 cntr_id, bool assign); >>>>>> +int rdtgroup_assign_cntr_event(struct rdt_resource *r, struct rdtgroup *rdtgrp, >>>>>> +                   struct rdt_mon_domain *d, enum resctrl_event_id evtid); >>>>>>   void rdt_staged_configs_clear(void); >>>>>>   bool closid_allocated(unsigned int closid); >>>>>>   int resctrl_find_cleanest_closid(void); >>>>>> diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/resctrl/rdtgroup.c >>>>>> index 1b5529c212f5..bc3752967c44 100644 >>>>>> --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c >>>>>> +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c >>>>>> @@ -1924,6 +1924,93 @@ int resctrl_arch_config_cntr(struct rdt_resource *r, struct rdt_mon_domain *d, >>>>>>       return 0; >>>>>>   } >>>>>>   +/* >>>>>> + * Configure the counter for the event, RMID pair for the domain. >>>>>> + * Update the bitmap and reset the architectural state. >>>>>> + */ >>>>>> +static int resctrl_config_cntr(struct rdt_resource *r, struct rdt_mon_domain *d, >>>>>> +                   enum resctrl_event_id evtid, u32 rmid, u32 closid, >>>>>> +                   u32 cntr_id, bool assign) >>>>>> +{ >>>>>> +    int ret; >>>>>> + >>>>>> +    ret = resctrl_arch_config_cntr(r, d, evtid, rmid, closid, cntr_id, assign); >>>>>> +    if (ret) >>>>>> +        return ret; >>>>>> + >>>>>> +    if (assign) >>>>>> +        __set_bit(cntr_id, d->mbm_cntr_map); >>>>>> +    else >>>>>> +        __clear_bit(cntr_id, d->mbm_cntr_map); >>>>>> + >>>>>> +    /* >>>>>> +     * Reset the architectural state so that reading of hardware >>>>>> +     * counter is not considered as an overflow in next update. >>>>>> +     */ >>>>>> +    resctrl_arch_reset_rmid(r, d, closid, rmid, evtid); >>>>> >>>>> resctrl_arch_reset_rmid() expects to be run on a CPU that is in the domain >>>>> @d ... note that after the architectural state is reset it initializes the >>>>> state by reading the event on the current CPU. By running it here it is >>>>> run on a random CPU that may not be in the right domain. >>>> >>>> Yes. That is correct.  We can move this part to our earlier >>>> implementation. We dont need to read the RMID.  We just have to reset the >>>> counter. >>>> >>>> https://lore.kernel.org/lkml/16d88cc4091cef1999b7ec329364e12dd0dc748d.1728495588.git.babu.moger@amd.com/ >>>> >>>> diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c >>>> b/arch/x86/kernel/cpu/resctrl/rdtgroup.c >>>> index 9fe419d0c536..bc3654ec3a08 100644 >>>> --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c >>>> +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c >>>> @@ -2371,6 +2371,13 @@ int resctrl_arch_config_cntr(struct rdt_resource >>>> *r, struct rdt_mon_domain *d, >>>>          smp_call_function_any(&d->hdr.cpu_mask, resctrl_abmc_config_one_amd, >>>>                                &abmc_cfg, 1); >>>> >>>> +       /* >>>> +        * Reset the architectural state so that reading of hardware >>>> +        * counter is not considered as an overflow in next update. >>>> +        */ >>>> +       if (arch_mbm) >>>> +               memset(arch_mbm, 0, sizeof(struct arch_mbm_state)); >>>> + >>>>          return 0; >>>>   } >>>> >>>> >>> >>> I am not sure what you envision here. One motivation for the move out of >>> resctrl_arch_config_cntr() was to avoid architectural state being reset twice. For reference, >>> mbm_config_write_domain()->resctrl_arch_reset_rmid_all(). Will architectural state >>> be reset twice again? >> >> That is good point. We don't have to do it twice. >> >> We can move the whole reset(arch_mbm) in  resctrl_arch_config_cntr(). > > This is not clear to me. The architectural state needs to be reset on MBM config write even > when assignable mode is not supported and/or enabled. Moving it to resctrl_arch_config_cntr() > will break this, no? Yes. The architectural state needs to be reset if ABMC is enabled or not enabled on MBM config write. > > I wonder if it may not simplify things to call resctrl_arch_reset_rmid() from > resctrl_abmc_config_one_amd()? Yes. That is is an option. I can try. > >>> One thing that I did not notice before is that the non-architectural MBM state is not >>> reset. Care should be taken to reset this also when considering that there is a plan >>> to use that MBM state to build a generic rate event for all platforms: >>> https://lore.kernel.org/all/CALPaoCgFRFgQqG00Uc0GhMHK47bsbtFw6Bxy5O9A_HeYmGa5sA@mail.gmail.com/ >> >> Did you mean we should add the following code in resctrl_arch_config_cntr()? >> >> m = get_mbm_state(d, closid, rmid, evtid); >> if (m) >>      memset(m, 0, sizeof(struct mbm_state)); > > This is not arch code but instead resctrl fs, so resctrl_config_cntr() may be more appropriate? Sure. We can do that. > > Reinette > > -- - Babu Moger