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b=vL/smArVv5bBygGzsq435saRnwJd0obq10DkKTTEs/8wC2FcD4S2nzg8+MGMS5KN4M1DhWMzp08QdW6+MRffwd72N+laEdBES14fwDHUZKfbsJZKhFpo3H6xfo3L1JfOeXqIohtWjghqcj6/aBoTaG+sBaoKe9pdgmWM5GKpkOk= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amd.com; Received: from SA1PR12MB6970.namprd12.prod.outlook.com (2603:10b6:806:24d::5) by MN2PR12MB4423.namprd12.prod.outlook.com (2603:10b6:208:24f::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.159.19; Mon, 29 Jun 2026 16:56:44 +0000 Received: from SA1PR12MB6970.namprd12.prod.outlook.com ([fe80::a65f:48fc:86fb:e958]) by SA1PR12MB6970.namprd12.prod.outlook.com ([fe80::a65f:48fc:86fb:e958%4]) with mapi id 15.21.0159.018; Mon, 29 Jun 2026 16:56:44 +0000 Message-ID: <3d303f39-433c-4ccb-aa99-9b832cefe435@amd.com> Date: Mon, 29 Jun 2026 12:57:23 -0400 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RFC 1/3] drm/amd/display: quirk malformed CH7218 PCON topology From: George Zhang To: stevester.codes@gmail.com, amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Harry Wentland , Leo Li , Rodrigo Siqueira , Alex Deucher , =?UTF-8?Q?Christian_K=C3=B6nig?= , David Airlie , Simona Vetter , =?UTF-8?Q?Tomasz_Paku=C5=82a?= , Mark.Broadworth@amd.com References: <20260620-ch7218-rfc-v1-b4-v1-1-3412debf44b6@gmail.com> Content-Language: en-US In-Reply-To: Content-Type: text/plain; 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This does not program the PCON or synthesize source-control > > FRL state. > > > > Signed-off-by: Stephen > > Hi Stephen, thank you for the patch. > > What dongle you are observing this issue on? We are interested in > reproducing the observed bug. > > Thanks, > George > Hi Stephen, We observed a hang/reboot due to these patches on DCN42 while testing DP2 Link Layer Compliance: - 4.3.1.23 - Successful Link Training to a Lower Bandwidth. When CDS_INTERLANE_ALIGN_DONE bit not set during CDS phase - 4.3.1.24 - UHBR Fallback rate table validation Tested on DCN42 with M42d compliance box via USB4 Thanks, George CC: Mark.Broadworth@amd.com > > --- > >   .../display/dc/link/protocols/link_dp_capability.c | 47 ++++++++++++ > > ++++++++-- > >   .../drm/amd/display/include/ddc_service_types.h    |  1 + > >   2 files changed, 45 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/ > > link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/ > > link_dp_capability.c > > index 47abb4066709..c2b48abfe7e6 100644 > > --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c > > +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c > > @@ -1158,6 +1158,31 @@ static void read_and_intersect_post_frl_lt_status( > >       } > >   } > > +static bool is_ch7218_pcon(const struct dc_link *link) > > +{ > > +    return link->dpcd_caps.branch_dev_id == > > DP_BRANCH_DEVICE_ID_2B02F0 && > > +        !memcmp(link->dpcd_caps.branch_dev_name, "CH7218", > > +            sizeof(link->dpcd_caps.branch_dev_name)); > > +} > > + > > +static void apply_ch7218_pcon_caps_quirk(struct dc_link *link) > > +{ > > +    if (!link->dc->caps.dp_hdmi21_pcon_support) > > +        return; > > + > > +    /* > > +     * Some CH7218 firmware reports no downstream port, or reports the > > +     * detailed downstream port as DP, while the device identity and > > EDID > > +     * describe a DP-to-HDMI 2.1 PCON. Restore only the documented > > converter > > +     * capability ceilings here; do not touch the PCON link state. > > +     */ > > +    link->dpcd_caps.dongle_caps.dp_hdmi_max_bpc = 12; > > +    link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps = > > 48000000; > > +    link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_pass_through = true; > > +    link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_pass_through = true; > > +    link->dpcd_caps.dongle_caps.extendedCapValid = true; > > +} > > + > >   static void get_active_converter_info( > >       uint8_t data, struct dc_link *link) > >   { > > @@ -1166,10 +1191,19 @@ static void get_active_converter_info( > >       /* decode converter info*/ > >       if (!ds_port.fields.PORT_PRESENT) { > > -        link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE; > > +        if (is_ch7218_pcon(link)) { > > +            link->dpcd_caps.is_branch_dev = true; > > +            link->dpcd_caps.dongle_type = > > +                DISPLAY_DONGLE_DP_HDMI_CONVERTER; > > +            link->dpcd_caps.dongle_caps.dongle_type = > > +                link->dpcd_caps.dongle_type; > > +            apply_ch7218_pcon_caps_quirk(link); > > +        } else { > > +            link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE; > > +            link->dpcd_caps.is_branch_dev = false; > > +        } > >           set_dongle_type(link->ddc, > >                   link->dpcd_caps.dongle_type); > > -        link->dpcd_caps.is_branch_dev = false; > >           return; > >       } > > @@ -1200,7 +1234,14 @@ static void get_active_converter_info( > >               switch (port_caps->bits.DWN_STRM_PORTX_TYPE) { > >               /*Handle DP case as DONGLE_NONE*/ > >               case DOWN_STREAM_DETAILED_DP: > > -                link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE; > > +                link->dpcd_caps.dongle_type = is_ch7218_pcon(link) ? > > +                    DISPLAY_DONGLE_DP_HDMI_CONVERTER : > > +                    DISPLAY_DONGLE_NONE; > > +                link->dpcd_caps.dongle_caps.dongle_type = > > +                    link->dpcd_caps.dongle_type; > > +                if (link->dpcd_caps.dongle_type == > > +                        DISPLAY_DONGLE_DP_HDMI_CONVERTER) > > +                    apply_ch7218_pcon_caps_quirk(link); > >                   break; > >               case DOWN_STREAM_DETAILED_VGA: > >                   link->dpcd_caps.dongle_type = > > diff --git a/drivers/gpu/drm/amd/display/include/ddc_service_types.h > > b/drivers/gpu/drm/amd/display/include/ddc_service_types.h > > index 53210e3aa0e0..4164f8a5ae56 100644 > > --- a/drivers/gpu/drm/amd/display/include/ddc_service_types.h > > +++ b/drivers/gpu/drm/amd/display/include/ddc_service_types.h > > @@ -37,6 +37,7 @@ > >   #define DP_BRANCH_DEVICE_ID_001CF8 0x001CF8 > >   #define DP_BRANCH_DEVICE_ID_0060AD 0x0060AD > >   #define DP_BRANCH_DEVICE_ID_001FF2 0x001FF2 > > +#define DP_BRANCH_DEVICE_ID_2B02F0 0x2B02F0 > >   #define DP_BRANCH_HW_REV_10 0x10 > >   #define DP_BRANCH_HW_REV_20 0x20 > > > >