[PATCH v5 10/13] ARM: dts: imx6ul: Share Variscite PHY clock and update PHY options

[Stefano Radaelli <stefano.radaelli21@gmail.com>]

From: Stefano Radaelli <stefano.r@variscite.com>

Move rmii_ref_clk from the ENET2 file to the VAR-SOM-6UL common
file. Symphony needs the same clock but must not include the
Concerto FEC2/MDIO configuration to obtain it.

Encode the Micrel RMII clock selection as <1> to match the updated
binding.

The existing Concerto descriptions hold PHY reset for 100 ms but
do not specify a delay after releasing it. Use the reset timing
validated by Variscite: assert reset for 10 ms and wait 100 ms
after deassertion before accessing the PHY. Apply this timing
through the shared Ethernet files to both the existing Concerto
boards and the new variants.

Signed-off-by: Stefano Radaelli <stefano.r@variscite.com>
---
v4->v5:
 - Replace the broad Concerto conversion patch with a focused Ethernet
   update. Move the audio, storage and carrier consumer updates into
   patches 7-9 alongside the corresponding shared-file changes.
 - Retain the existing ENET1 and ENET2 option files and move the PHY
   reference clock into the module common file for Symphony to reuse.
 - Encode the Micrel clock-selection property as <1> and apply the
   validated 10 ms assert / 100 ms post-deassert timing through the
   shared Ethernet files, including the existing Concerto boards.

v2->v3:
 - Use the shared storage and wireless option DTSI files.

v1->v2:
 - Use the shared WM8904 codec DTSI in the existing Concerto boards.

 .../dts/nxp/imx/imx6ul-var-som-common.dtsi    |  8 ++++++++
 .../dts/nxp/imx/imx6ul-var-som-enet1.dtsi     |  6 ++++--
 .../dts/nxp/imx/imx6ul-var-som-enet2.dtsi     | 19 ++++++-------------
 3 files changed, 18 insertions(+), 15 deletions(-)

diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
index d2a9877344ce..ef838ae07297 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
@@ -20,6 +20,14 @@ memory@80000000 {
 		reg = <0x80000000 0x20000000>;
 	};
 
+	/* ref_clk for micrel ethernet phy */
+	rmii_ref_clk: rmii-ref-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <25000000>;
+		clock-output-names = "rmii-ref";
+	};
+
 	reg_3p3v: regulator-3p3v {
 		compatible = "regulator-fixed";
 		regulator-name = "3P3V";
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet1.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet1.dtsi
index 6b1e34347bec..ace6d9f35b87 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet1.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet1.dtsi
@@ -5,6 +5,7 @@
  *
  * Copyright 2019-2024 Variscite Ltd.
  * Copyright 2026 Dimonoff
+ * Copyright (C) 2026 Variscite Ltd.
  */
 
 &fec1 {
@@ -37,8 +38,9 @@ ethphy0: ethernet-phy@1 {
 		clocks = <&rmii_ref_clk>;
 		clock-names = "rmii-ref";
 		reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
-		reset-assert-us = <100000>;
+		reset-assert-us = <10000>;
+		reset-deassert-us = <100000>;
 		micrel,led-mode = <1>;
-		micrel,rmii-reference-clock-select-25-mhz;
+		micrel,rmii-reference-clock-select-25-mhz = <1>;
 	};
 };
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet2.dtsi
index f0ed71798617..a207a720bd30 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet2.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet2.dtsi
@@ -7,15 +7,6 @@
  * Copyright (C) 2026 Variscite Ltd.
  */
 
-/ {
-	rmii_ref_clk: rmii-ref-clk {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <25000000>;
-		clock-output-names = "rmii-ref";
-	};
-};
-
 &fec2 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_enet2>, <&pinctrl_enet2_gpio>, <&pinctrl_enet2_mdio>;
@@ -33,9 +24,10 @@ ethphy0: ethernet-phy@1 {
 			clocks = <&rmii_ref_clk>;
 			clock-names = "rmii-ref";
 			reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
-			reset-assert-us = <100000>;
+			reset-assert-us = <10000>;
+			reset-deassert-us = <100000>;
 			micrel,led-mode = <1>;
-			micrel,rmii-reference-clock-select-25-mhz;
+			micrel,rmii-reference-clock-select-25-mhz = <1>;
 		};
 
 		ethphy1: ethernet-phy@3 {
@@ -44,9 +36,10 @@ ethphy1: ethernet-phy@3 {
 			clocks = <&rmii_ref_clk>;
 			clock-names = "rmii-ref";
 			reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>;
-			reset-assert-us = <100000>;
+			reset-assert-us = <10000>;
+			reset-deassert-us = <100000>;
 			micrel,led-mode = <0>;
-			micrel,rmii-reference-clock-select-25-mhz;
+			micrel,rmii-reference-clock-select-25-mhz = <1>;
 		};
 	};
 };
-- 
2.47.3