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Fri, 14 Aug 2026 04:05:51 -0700 (PDT) X-Received: by 2002:aa7:8681:0:b0:850:a86b:6ce1 with SMTP id d2e1a72fcca58-850a86b8ac4mr1694141b3a.0.1786705550748; Fri, 14 Aug 2026 04:05:50 -0700 (PDT) Received: from [10.92.210.190] ([202.46.23.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-8517d01f300sm312585b3a.18.2026.08.14.04.05.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 14 Aug 2026 04:05:50 -0700 (PDT) Message-ID: <3d8101b2-558b-48e0-badd-a8e439c74dd0@oss.qualcomm.com> Date: Fri, 14 Aug 2026 16:35:43 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/4] dt-bindings: arm: ras: Introduce bindings for ARM RAS error sources To: Krzysztof Kozlowski , Trilok Soni Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Ruidong Tian , Tony Luck , Borislav Petkov , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, faruque.ansari@oss.qualcomm.com, avaneesh.dwivedi@oss.qualcomm.com References: <20260720081954.1858180-1-umang.chheda@oss.qualcomm.com> <20260720081954.1858180-2-umang.chheda@oss.qualcomm.com> <20260728-determined-lorikeet-from-tartarus-cf124e@quoll> Content-Language: en-US From: Umang Chheda In-Reply-To: <20260728-determined-lorikeet-from-tartarus-cf124e@quoll> Content-Type: text/plain; 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This is not a right approach. >> > > Is this page size or register window page size? If the latter, why would > device registers be a binding? Thanks for the review. To clarify both points: On "page size" vs "register window page size": The comment in arm-ras.h is misleading — I will fix it. It is neither a memory page size nor a kernel page granularity. The 4K/16K/64K values refer to the three fixed error record group register window layouts defined by the ARM RAS architecture specification. The naming comes from the ARM spec itself which uses these sizes to describe the three possible layouts of the MMIO window. I will update the comment to make this clear. On "why would device registers be a binding": This is a static hardware property — it describes which of the three fixed register layouts the hardware block implements, and it is not self-discoverable at runtime. There is no register within the window that encodes the layout. The driver needs it upfront to: - Determine the correct ioremap size - Know how many ERRGSR registers to scan - Know the array length for arm,record-impl and arm,status-reporting I will also fix the misleading comment in arm-ras.h from "register window page size" to "error record group register window layout" in v3. > > Best regards, > Krzysztof > Thanks, Umang