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Tue, 11 Nov 2025 08:53:19 -0800 (PST) Received: from [192.168.10.81] ([176.206.111.214]) by smtp.googlemail.com with ESMTPSA id a640c23a62f3a-b72bf97d430sm1451420666b.37.2025.11.11.08.53.17 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 11 Nov 2025 08:53:18 -0800 (PST) Message-ID: <3d93c8bc-8f13-42e1-a9e1-0d27d7e8603b@redhat.com> Date: Tue, 11 Nov 2025 17:53:06 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RFC v1 12/20] KVM: x86: Support REX2-extended register index in the decoder To: "Chang S. Bae" , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: seanjc@google.com, chao.gao@intel.com, zhao1.liu@intel.com References: <20251110180131.28264-1-chang.seok.bae@intel.com> <20251110180131.28264-13-chang.seok.bae@intel.com> From: Paolo Bonzini Content-Language: en-US Autocrypt: addr=pbonzini@redhat.com; keydata= xsEhBFRCcBIBDqDGsz4K0zZun3jh+U6Z9wNGLKQ0kSFyjN38gMqU1SfP+TUNQepFHb/Gc0E2 CxXPkIBTvYY+ZPkoTh5xF9oS1jqI8iRLzouzF8yXs3QjQIZ2SfuCxSVwlV65jotcjD2FTN04 hVopm9llFijNZpVIOGUTqzM4U55sdsCcZUluWM6x4HSOdw5F5Utxfp1wOjD/v92Lrax0hjiX DResHSt48q+8FrZzY+AUbkUS+Jm34qjswdrgsC5uxeVcLkBgWLmov2kMaMROT0YmFY6A3m1S P/kXmHDXxhe23gKb3dgwxUTpENDBGcfEzrzilWueOeUWiOcWuFOed/C3SyijBx3Av/lbCsHU Vx6pMycNTdzU1BuAroB+Y3mNEuW56Yd44jlInzG2UOwt9XjjdKkJZ1g0P9dwptwLEgTEd3Fo UdhAQyRXGYO8oROiuh+RZ1lXp6AQ4ZjoyH8WLfTLf5g1EKCTc4C1sy1vQSdzIRu3rBIjAvnC tGZADei1IExLqB3uzXKzZ1BZ+Z8hnt2og9hb7H0y8diYfEk2w3R7wEr+Ehk5NQsT2MPI2QBd wEv1/Aj1DgUHZAHzG1QN9S8wNWQ6K9DqHZTBnI1hUlkp22zCSHK/6FwUCuYp1zcAEQEAAc0j UGFvbG8gQm9uemluaSA8cGJvbnppbmlAcmVkaGF0LmNvbT7CwU0EEwECACMFAlRCcBICGwMH CwkIBwMCAQYVCAIJCgsEFgIDAQIeAQIXgAAKCRB+FRAMzTZpsbceDp9IIN6BIA0Ol7MoB15E 11kRz/ewzryFY54tQlMnd4xxfH8MTQ/mm9I482YoSwPMdcWFAKnUX6Yo30tbLiNB8hzaHeRj jx12K+ptqYbg+cevgOtbLAlL9kNgLLcsGqC2829jBCUTVeMSZDrzS97ole/YEez2qFpPnTV0 VrRWClWVfYh+JfzpXmgyhbkuwUxNFk421s4Ajp3d8nPPFUGgBG5HOxzkAm7xb1cjAuJ+oi/K CHfkuN+fLZl/u3E/fw7vvOESApLU5o0icVXeakfSz0LsygEnekDbxPnE5af/9FEkXJD5EoYG SEahaEtgNrR4qsyxyAGYgZlS70vkSSYJ+iT2rrwEiDlo31MzRo6Ba2FfHBSJ7lcYdPT7bbk9 AO3hlNMhNdUhoQv7M5HsnqZ6unvSHOKmReNaS9egAGdRN0/GPDWr9wroyJ65ZNQsHl9nXBqE AukZNr5oJO5vxrYiAuuTSd6UI/xFkjtkzltG3mw5ao2bBpk/V/YuePrJsnPFHG7NhizrxttB nTuOSCMo45pfHQ+XYd5K1+Cv/NzZFNWscm5htJ0HznY+oOsZvHTyGz3v91pn51dkRYN0otqr bQ4tlFFuVjArBZcapSIe6NV8C4cEiSTOwE0EVEJx7gEIAMeHcVzuv2bp9HlWDp6+RkZe+vtl KwAHplb/WH59j2wyG8V6i33+6MlSSJMOFnYUCCL77bucx9uImI5nX24PIlqT+zasVEEVGSRF m8dgkcJDB7Tps0IkNrUi4yof3B3shR+vMY3i3Ip0e41zKx0CvlAhMOo6otaHmcxr35sWq1Jk tLkbn3wG+fPQCVudJJECvVQ//UAthSSEklA50QtD2sBkmQ14ZryEyTHQ+E42K3j2IUmOLriF dNr9NvE1QGmGyIcbw2NIVEBOK/GWxkS5+dmxM2iD4Jdaf2nSn3jlHjEXoPwpMs0KZsgdU0pP JQzMUMwmB1wM8JxovFlPYrhNT9MAEQEAAcLBMwQYAQIACQUCVEJx7gIbDAAKCRB+FRAMzTZp sadRDqCctLmYICZu4GSnie4lKXl+HqlLanpVMOoFNnWs9oRP47MbE2wv8OaYh5pNR9VVgyhD OG0AU7oidG36OeUlrFDTfnPYYSF/mPCxHttosyt8O5kabxnIPv2URuAxDByz+iVbL+RjKaGM GDph56ZTswlx75nZVtIukqzLAQ5fa8OALSGum0cFi4ptZUOhDNz1onz61klD6z3MODi0sBZN Aj6guB2L/+2ZwElZEeRBERRd/uommlYuToAXfNRdUwrwl9gRMiA0WSyTb190zneRRDfpSK5d usXnM/O+kr3Dm+Ui+UioPf6wgbn3T0o6I5BhVhs4h4hWmIW7iNhPjX1iybXfmb1gAFfjtHfL xRUr64svXpyfJMScIQtBAm0ihWPltXkyITA92ngCmPdHa6M1hMh4RDX+Jf1fiWubzp1voAg0 JBrdmNZSQDz0iKmSrx8xkoXYfA3bgtFN8WJH2xgFL28XnqY4M6dLhJwV3z08tPSRqYFm4NMP dRsn0/7oymhneL8RthIvjDDQ5ktUjMe8LtHr70OZE/TT88qvEdhiIVUogHdo4qBrk41+gGQh b906Dudw5YhTJFU3nC6bbF2nrLlB4C/XSiH76ZvqzV0Z/cAMBo5NF/w= In-Reply-To: <20251110180131.28264-13-chang.seok.bae@intel.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 11/10/25 19:01, Chang S. Bae wrote: > Update register index decoding to account for the additional bit fields > introduced by the REX2 prefix. > > Both ModR/M and opcode register decoding paths now consider the extended > index bits (R4, X4, B4) in addition to the legacy REX bits (R3, X3, B3). > > Signed-off-by: Chang S. Bae Replying here for both patches 10 and 12, because I think you can merge them in one, I'd prefer to avoid bitfields. You only need a single enum: enum { REX_B = 1, REX_X = 2, REX_R = 4, REX_W = 8, REX_M = 0x80, }; for REX_W/REX_M you access them directly, while for RXB you go through a function: static inline rex_get_rxb(u8 rex, u8 fld) { BUILD_BUG_ON(!__builtin_constant_p(fld)); BUILD_BUG_ON(fld != REX_B && fld != REX_X && fld != REX_R); rex >>= ffs(fld) - 1; // bits 0+4 return (rex & 1) + (rex & 0x10 ? 8 : 0); } > } else { > reg = (ctxt->b & 7) | > - (ctxt->rex.bits.b3 * BIT(3)); > + (ctxt->rex.bits.b3 * BIT(3)) | > + (ctxt->rex.bits.b4 * BIT(4)); + rex_get_rxb(ctxt->rex, REX_B); and likewise everywhere else. > } > > if (ctxt->d & Sse) { > @@ -1124,9 +1125,12 @@ static int decode_modrm(struct x86_emulate_ctxt *ctxt, > int rc = X86EMUL_CONTINUE; > ulong modrm_ea = 0; > > - ctxt->modrm_reg = ctxt->rex.bits.r3 * BIT(3); > - index_reg = ctxt->rex.bits.x3 * BIT(3); > - base_reg = ctxt->rex.bits.b3 * BIT(3); > + ctxt->modrm_reg = (ctxt->rex.bits.r3 * BIT(3)) | > + (ctxt->rex.bits.r4 * BIT(4)); > + index_reg = (ctxt->rex.bits.x3 * BIT(3)) | > + (ctxt->rex.bits.x4 * BIT(4)); > + base_reg = (ctxt->rex.bits.b3 * BIT(3)) | > + (ctxt->rex.bits.b4 * BIT(4)); > > ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6; > ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;