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Mon, 25 Nov 2024 21:31:59 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4APLVxEG014067 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 25 Nov 2024 21:31:59 GMT Received: from [10.71.111.113] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 25 Nov 2024 13:31:58 -0800 Message-ID: <3d9d3d18-9028-4dbc-8e72-3ed70edc97f4@quicinc.com> Date: Mon, 25 Nov 2024 13:31:58 -0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 5/7] clk: qcom: Add support for GCC clock controller on SM8750 To: Dmitry Baryshkov CC: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Trilok Soni , Satya Durga Srinivasu Prabhala , , , , References: <20241112002807.2804021-1-quic_molvera@quicinc.com> <20241112002807.2804021-6-quic_molvera@quicinc.com> Content-Language: en-US From: Melody Olvera In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: u84ly2cQOz28e0ZxANsHhkMfFhqz4kIs X-Proofpoint-ORIG-GUID: u84ly2cQOz28e0ZxANsHhkMfFhqz4kIs X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 bulkscore=0 suspectscore=0 spamscore=0 malwarescore=0 phishscore=0 clxscore=1015 impostorscore=0 mlxlogscore=999 adultscore=0 lowpriorityscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411250179 On 11/18/2024 5:59 PM, Dmitry Baryshkov wrote: > On Mon, Nov 18, 2024 at 11:30:58AM -0800, Melody Olvera wrote: >> >> On 11/15/2024 7:34 AM, Dmitry Baryshkov wrote: >>> On Mon, Nov 11, 2024 at 04:28:05PM -0800, Melody Olvera wrote: >>>> From: Taniya Das >>>> >>>> Add support for GCC Clock Controller for SM8750 platform. >>>> >>>> Signed-off-by: Taniya Das >>>> Signed-off-by: Melody Olvera >>>> --- >>>> drivers/clk/qcom/Kconfig | 9 + >>>> drivers/clk/qcom/Makefile | 1 + >>>> drivers/clk/qcom/gcc-sm8750.c | 3274 +++++++++++++++++++++++++++++++++ >>>> 3 files changed, 3284 insertions(+) >>>> create mode 100644 drivers/clk/qcom/gcc-sm8750.c >>>> >>>> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig >>>> index ef89d686cbc4..26bfb607235b 100644 >>>> --- a/drivers/clk/qcom/Kconfig >>>> +++ b/drivers/clk/qcom/Kconfig >>>> @@ -1130,6 +1130,15 @@ config SM_GCC_8650 >>>> Say Y if you want to use peripheral devices such as UART, >>>> SPI, I2C, USB, SD/UFS, PCIe etc. >>>> +config SM_GCC_8750 >>>> + tristate "SM8750 Global Clock Controller" >>>> + depends on ARM64 || COMPILE_TEST >>>> + select QCOM_GDSC >>>> + help >>>> + Support for the global clock controller on SM8750 devices. >>>> + Say Y if you want to use peripheral devices such as UART, >>>> + SPI, I2C, USB, SD/UFS, PCIe etc. >>>> + >>>> config SM_GPUCC_4450 >>>> tristate "SM4450 Graphics Clock Controller" >>>> depends on ARM64 || COMPILE_TEST >>>> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile >>>> index b09dbdc210eb..1875018d1100 100644 >>>> --- a/drivers/clk/qcom/Makefile >>>> +++ b/drivers/clk/qcom/Makefile >>>> @@ -143,6 +143,7 @@ obj-$(CONFIG_SM_GCC_8350) += gcc-sm8350.o >>>> obj-$(CONFIG_SM_GCC_8450) += gcc-sm8450.o >>>> obj-$(CONFIG_SM_GCC_8550) += gcc-sm8550.o >>>> obj-$(CONFIG_SM_GCC_8650) += gcc-sm8650.o >>>> +obj-$(CONFIG_SM_GCC_8750) += gcc-sm8750.o >>>> obj-$(CONFIG_SM_GPUCC_4450) += gpucc-sm4450.o >>>> obj-$(CONFIG_SM_GPUCC_6115) += gpucc-sm6115.o >>>> obj-$(CONFIG_SM_GPUCC_6125) += gpucc-sm6125.o >>>> diff --git a/drivers/clk/qcom/gcc-sm8750.c b/drivers/clk/qcom/gcc-sm8750.c >>>> new file mode 100644 >>>> index 000000000000..faaefa42a039 >>>> --- /dev/null >>>> +++ b/drivers/clk/qcom/gcc-sm8750.c >>>> @@ -0,0 +1,3274 @@ >>>> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >>>> +/* >>>> + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. >>>> + */ >>>> + >>>> +#include >>>> +#include >>>> +#include >>>> +#include >>>> +#include >>>> + >>>> +#include >>>> + >>>> +#include "clk-alpha-pll.h" >>>> +#include "clk-branch.h" >>>> +#include "clk-pll.h" >>>> +#include "clk-rcg.h" >>>> +#include "clk-regmap.h" >>>> +#include "clk-regmap-divider.h" >>>> +#include "clk-regmap-mux.h" >>>> +#include "clk-regmap-phy-mux.h" >>>> +#include "common.h" >>>> +#include "gdsc.h" >>>> +#include "reset.h" >>>> + >>>> +enum { >>>> + DT_BI_TCXO, >>>> + DT_BI_TCXO_AO, >>>> + DT_PCIE_0_PIPE_CLK, >>>> + DT_SLEEP_CLK, >>>> + DT_UFS_PHY_RX_SYMBOL_0_CLK, >>>> + DT_UFS_PHY_RX_SYMBOL_1_CLK, >>>> + DT_UFS_PHY_TX_SYMBOL_0_CLK, >>>> + DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, >>> This doesn't match Documentation/devicetree/bindings/clock/qcom,sm8650-gcc.yaml >> Hmmm I see what seems to have happened here. You're correct; this doesn't >> match the bindings >> in sm8650-gcc. The v1 patchset had a new bindings file which matched the >> sm8650 bindings, but also >> didn't match the driver; however we only seemed to catch that the two >> bindings matched and not the >> fact that they didn't match the drivers. > I don't see v1. Please bring bindings back. Will do. > >> In terms of remedy I see two options. I'm fairly certain the driver here is >> correct, so we can either >> add the sm8750 bindings file back and remove the two lines about the PCIE 1 >> clocks or adjust the >> sm8650 binding to encompass both sm8650 and sm8750. It's unclear to me how >> precedented the latter >> is; certainly having a single bindings file encompass both chips is >> feasible, but I think I'm currently >> leaning towards bringing back the original bindings file as that seems more >> precedented. Lmk >> your thoughts. > How are you thinking to change SM8650 bindings without breaking the ABI > / backwards compatibility? Giant if-then (read: poorly). Thanks, Melody