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Thu, 14 Aug 2025 03:52:59 -0700 (PDT) Message-ID: <3da37a91-9512-405b-ba74-c1feb80b4dd2@linaro.org> Date: Thu, 14 Aug 2025 11:52:58 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] coresight-etm4x: Conditionally access register TRCEXTINSELR To: Mike Leach Cc: Yuanfang Zhang , kernel@oss.qualcomm.com, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Suzuki K Poulose , Alexander Shishkin References: <20250812-trcextinselr_issue-v2-1-e6eb121dfcf4@oss.qualcomm.com> <272077d5-12b1-4922-b924-a96c34b3b1c9@linaro.org> Content-Language: en-US From: James Clark In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 14/08/2025 11:25 am, Mike Leach wrote: > On Thu, 14 Aug 2025 at 10:51, James Clark wrote: >> >> >> >> On 12/08/2025 9:24 am, Yuanfang Zhang wrote: >>> The TRCEXTINSELR is only implemented if TRCIDR5.NUMEXTINSEL > 0. >>> To avoid invalid accesses, introduce a check on numextinsel >>> (derived from TRCIDR5[11:9]) before reading or writing to this register. >>> >>> Fixes: f5bd523690d2 ("coresight: etm4x: Convert all register accesses") >> >> This tag isn't right. Although this is where the register accesses were >> last touched, the root issue was present from the introduction of the >> driver. >> > > Memory mapped access to unimplemented registers are RES0 so won't fail > - the issue is the system register access where an undefined exception > can be triggered. > > Mike > Ah, good point. I assumed that commit was just a refactor.