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From: "Thomas Hellström" <thomas.hellstrom@linux.intel.com>
To: Robert Beckett <bob.beckett@collabora.com>,
	dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org,
	Jani Nikula <jani.nikula@linux.intel.com>,
	Joonas Lahtinen <joonas.lahtinen@linux.intel.com>,
	Rodrigo Vivi <rodrigo.vivi@intel.com>,
	Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>,
	David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>
Cc: kernel@collabora.com, Matthew Auld <matthew.auld@intel.com>,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v8 01/10] drm/i915/ttm: dont trample cache_level overrides during ttm move
Date: Wed, 22 Jun 2022 12:44:59 +0200	[thread overview]
Message-ID: <3dae0d34-78f3-b74e-517d-f14274540cf1@linux.intel.com> (raw)
In-Reply-To: <20220621200058.3536182-2-bob.beckett@collabora.com>


On 6/21/22 22:00, Robert Beckett wrote:
> Various places within the driver override the default chosen cache_level.
> Before ttm, these overrides were permanent until explicitly changed again
> or for the lifetime of the buffer.
>
> TTM movement code came along and decided that it could make that
> decision at that time, which is usually well after object creation, so
> overrode the cache_level decision and reverted it back to its default
> decision.
>
> Add logic to indicate whether the caching mode has been set by anything
> other than the move logic. If so, assume that the code that overrode the
> defaults knows best and keep it.
>
> Signed-off-by: Robert Beckett <bob.beckett@collabora.com>

LGTM.

Reviewed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>


> ---
>   drivers/gpu/drm/i915/gem/i915_gem_object.c       | 1 +
>   drivers/gpu/drm/i915/gem/i915_gem_object_types.h | 1 +
>   drivers/gpu/drm/i915/gem/i915_gem_ttm.c          | 1 +
>   drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c     | 9 ++++++---
>   4 files changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c b/drivers/gpu/drm/i915/gem/i915_gem_object.c
> index 06b1b188ce5a..519887769c08 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
> @@ -125,6 +125,7 @@ void i915_gem_object_set_cache_coherency(struct drm_i915_gem_object *obj,
>   	struct drm_i915_private *i915 = to_i915(obj->base.dev);
>   
>   	obj->cache_level = cache_level;
> +	obj->ttm.cache_level_override = true;
>   
>   	if (cache_level != I915_CACHE_NONE)
>   		obj->cache_coherent = (I915_BO_CACHE_COHERENT_FOR_READ |
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> index 2c88bdb8ff7c..6632ed52e919 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> @@ -605,6 +605,7 @@ struct drm_i915_gem_object {
>   		struct i915_gem_object_page_iter get_io_page;
>   		struct drm_i915_gem_object *backup;
>   		bool created:1;
> +		bool cache_level_override:1;
>   	} ttm;
>   
>   	/*
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
> index 4c25d9b2f138..27d59639177f 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
> @@ -1241,6 +1241,7 @@ int __i915_gem_ttm_object_init(struct intel_memory_region *mem,
>   	i915_gem_object_init_memory_region(obj, mem);
>   	i915_ttm_adjust_domains_after_move(obj);
>   	i915_ttm_adjust_gem_after_move(obj);
> +	obj->ttm.cache_level_override = false;
>   	i915_gem_object_unlock(obj);
>   
>   	return 0;
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
> index a10716f4e717..4c1de0b4a10f 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
> @@ -123,9 +123,12 @@ void i915_ttm_adjust_gem_after_move(struct drm_i915_gem_object *obj)
>   	obj->mem_flags |= i915_ttm_cpu_maps_iomem(bo->resource) ? I915_BO_FLAG_IOMEM :
>   		I915_BO_FLAG_STRUCT_PAGE;
>   
> -	cache_level = i915_ttm_cache_level(to_i915(bo->base.dev), bo->resource,
> -					   bo->ttm);
> -	i915_gem_object_set_cache_coherency(obj, cache_level);
> +	if (!obj->ttm.cache_level_override) {
> +		cache_level = i915_ttm_cache_level(to_i915(bo->base.dev),
> +						   bo->resource, bo->ttm);
> +		i915_gem_object_set_cache_coherency(obj, cache_level);
> +		obj->ttm.cache_level_override = false;
> +	}
>   }
>   
>   /**

  reply	other threads:[~2022-06-22 10:45 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <20220621200058.3536182-1-bob.beckett@collabora.com>
2022-06-21 20:00 ` Robert Beckett
2022-06-22 10:44   ` Thomas Hellström [this message]
2022-06-21 20:00 ` [PATCH v8 02/10] drm/i915: limit ttm to dma32 for i965G[M] Robert Beckett
2022-06-22 10:45   ` Thomas Hellström
2022-06-21 20:00 ` [PATCH v8 03/10] drm/i915/ttm: only trust snooping for dgfx when deciding default cache_level Robert Beckett
2022-06-22 10:50   ` Thomas Hellström
2022-06-21 20:00 ` [PATCH v8 04/10] drm/i915/gem: selftest should not attempt mmap of private regions Robert Beckett
2022-06-22 11:37   ` Thomas Hellström
2022-06-21 20:00 ` [PATCH v8 05/10] drm/i915: instantiate ttm ranger manager for stolen memory Robert Beckett
2022-06-21 20:00 ` [PATCH v8 06/10] drm/i915: sanitize mem_flags for stolen buffers Robert Beckett
2022-06-21 20:00 ` [PATCH v8 07/10] drm/i915: ttm move/clear logic fix Robert Beckett
2022-06-21 20:00 ` [PATCH v8 08/10] drm/i915: allow memory region creators to alloc and free the region Robert Beckett
2022-06-22 11:55   ` Thomas Hellström
2022-06-21 20:00 ` [PATCH v8 09/10] drm/i915/ttm: add buffer pin on alloc flag Robert Beckett
2022-06-21 20:00 ` [PATCH v8 10/10] drm/i915: stolen memory use ttm backend Robert Beckett

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