From: Sibi Sankar <quic_sibis@quicinc.com>
To: Konrad Dybcio <konrad.dybcio@linaro.org>, <andersson@kernel.org>,
<robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
<catalin.marinas@arm.com>, <ulf.hansson@linaro.org>
Cc: <agross@kernel.org>, <conor+dt@kernel.org>,
<ayan.kumar.halder@amd.com>, <j@jannau.net>,
<dmitry.baryshkov@linaro.org>, <nfraprado@collabora.com>,
<m.szyprowski@samsung.com>, <u-kumar1@ti.com>, <peng.fan@nxp.com>,
<lpieralisi@kernel.org>, <quic_rjendra@quicinc.com>,
<abel.vesa@linaro.org>, <linux-arm-msm@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>, <quic_tsoni@quicinc.com>,
<neil.armstrong@linaro.org>
Subject: Re: [PATCH V2 3/5] arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts
Date: Wed, 29 Nov 2023 14:55:40 +0530 [thread overview]
Message-ID: <3dd41426-c026-a832-0a6b-0aabfaec2a8c@quicinc.com> (raw)
In-Reply-To: <918ff1f5-ce01-43ea-b034-e69fbb31f495@linaro.org>
On 11/18/23 06:36, Konrad Dybcio wrote:
> On 17.11.2023 12:39, Sibi Sankar wrote:
>> From: Rajendra Nayak <quic_rjendra@quicinc.com>
>>
>> Add base dtsi and QCP board (Qualcomm Compute Platform) dts file for
>> X1E80100 SoC, describing the CPUs, GCC and RPMHCC clock controllers,
>> geni UART, interrupt controller, TLMM, reserved memory, interconnects,
>> SMMU and LLCC nodes.
>>
>> Co-developed-by: Abel Vesa <abel.vesa@linaro.org>
>> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
>> Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com>
>> Co-developed-by: Sibi Sankar <quic_sibis@quicinc.com>
>> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
>> ---
> [...]
>
>> +&tlmm {
>> + gpio-reserved-ranges = <33 3>, <44 4>, /* SPI (TPM) */
> Surely SPI doesn't use 7 wires! :D
yeah, they are just secure reserved unused gpios.
>
> [...]
>
>> + L2_0: l2-cache-0 {
> the cache device is distinguishable by its parent, so "l2-cache" is enough
thanks will fix ^^
>
>
>> + compatible = "cache";
>> + cache-level = <2>;
>> + cache-unified;
>> + };
>> + };
>> +
> [...]
>
>> + idle-states {
>> + entry-method = "psci";
>> +
>> + CLUSTER_C4: cpu-sleep-0 {
>> + compatible = "arm,idle-state";
>> + idle-state-name = "ret";
>> + arm,psci-suspend-param = <0x00000004>;
> These suspend parameters look funky.. is this just a PSCI sleep
> implementation that strays far away from Arm's suggested guidelines?
not really! it's just that 30th bit is set according to spec i.e
it's marked as a retention state.
>
> [...]
>
>
>> + CPU_PD11: power-domain-cpu11 {
>> + #power-domain-cells = <0>;
>> + power-domains = <&CLUSTER_PD>;
>> + };
>> +
>> + CLUSTER_PD: power-domain-cpu-cluster {
>> + #power-domain-cells = <0>;
>> + domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>;
>> + };
> So, can the 3 clusters not shut down their L2 and PLLs (if separate?)
> on their own?
on CL5 the clusters are expected to shutdown their l2 and PLL on their
own.
>
>> + };
>> +
>> + reserved-memory {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> +
>> + gunyah_hyp_mem: gunyah-hyp@80000000 {
>> + reg = <0x0 0x80000000 0x0 0x800000>;
>> + no-map;
>> + };
>> +
>> + hyp_elf_package_mem: hyp-elf_package@80800000 {
> no underscores in node names, use hyphens
ack
-Sibi
>
> The rest looks OK I think
>
> Konrad
next prev parent reply other threads:[~2023-11-29 9:26 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-17 11:39 [PATCH V2 0/5] dts: qcom: Introduce X1E80100 platforms device tree Sibi Sankar
2023-11-17 11:39 ` [PATCH V2 1/5] dt-bindings: arm: cpus: Add qcom,oryon compatible Sibi Sankar
2023-11-19 15:59 ` Rob Herring
2023-11-20 6:44 ` Sibi Sankar
2023-11-29 10:37 ` Sibi Sankar
2023-11-17 11:39 ` [PATCH V2 2/5] dt-bindings: arm: qcom: Document X1E80100 SoC and boards Sibi Sankar
2023-11-20 9:11 ` Krzysztof Kozlowski
2023-11-17 11:39 ` [PATCH V2 3/5] arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts Sibi Sankar
2023-11-18 1:06 ` Konrad Dybcio
2023-11-29 9:25 ` Sibi Sankar [this message]
2023-11-29 12:54 ` Konrad Dybcio
2023-11-29 15:46 ` Sibi Sankar
2023-11-29 22:29 ` Konrad Dybcio
2023-11-30 11:23 ` Sibi Sankar
2023-11-21 7:20 ` kernel test robot
2023-11-21 14:03 ` kernel test robot
2023-11-17 11:39 ` [PATCH V2 4/5] arm64: dts: qcom: x1e80100: Add Compute Reference Device Sibi Sankar
2023-11-18 1:07 ` Konrad Dybcio
2023-11-20 6:51 ` Sibi Sankar
2023-11-20 11:54 ` Konrad Dybcio
2023-11-20 9:04 ` Abel Vesa
2023-11-17 11:39 ` [PATCH V2 5/5] arm64: defconfig: Enable X1E80100 SoC base configs Sibi Sankar
2023-11-20 9:12 ` Krzysztof Kozlowski
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=3dd41426-c026-a832-0a6b-0aabfaec2a8c@quicinc.com \
--to=quic_sibis@quicinc.com \
--cc=abel.vesa@linaro.org \
--cc=agross@kernel.org \
--cc=andersson@kernel.org \
--cc=ayan.kumar.halder@amd.com \
--cc=catalin.marinas@arm.com \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=dmitry.baryshkov@linaro.org \
--cc=j@jannau.net \
--cc=konrad.dybcio@linaro.org \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=lpieralisi@kernel.org \
--cc=m.szyprowski@samsung.com \
--cc=neil.armstrong@linaro.org \
--cc=nfraprado@collabora.com \
--cc=peng.fan@nxp.com \
--cc=quic_rjendra@quicinc.com \
--cc=quic_tsoni@quicinc.com \
--cc=robh+dt@kernel.org \
--cc=u-kumar1@ti.com \
--cc=ulf.hansson@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®