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From: Benjamin Gaignard <benjamin.gaignard@collabora.com>
To: Nicolas Dufresne <nicolas@ndufresne.ca>,
	ezequiel@vanguardiasur.com.ar, p.zabel@pengutronix.de,
	mchehab@kernel.org, heiko@sntech.de
Cc: linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, kernel@collabora.com
Subject: Re: [PATCH] media: verisilicon: Fix auxiliary buffers allocation size
Date: Mon, 6 May 2024 16:38:35 +0200	[thread overview]
Message-ID: <3dde932a-1b62-4824-a9e0-722f82faaaa6@collabora.com> (raw)
In-Reply-To: <2a3b897a-71f7-4a94-a13c-1aa8b2d96e78@collabora.com>


Le 05/04/2024 à 10:13, Benjamin Gaignard a écrit :
>
> Le 04/04/2024 à 20:00, Nicolas Dufresne a écrit :
>> Hi,
>>
>> Le jeudi 28 mars 2024 à 10:34 +0100, Benjamin Gaignard a écrit :
>>> Use v4l2_av1_tile_info->tile_cols to know the number of colons
>>> in the frame. This made auxiliary buffers meory size computation
>>> more accurate.
>> Seems like this is potentially going to impact some conformance 
>> tests. Anything
>> to report from fluster results ?
>
> Flusters AV1 score is the same.
> Maybe we have been lucky when allocating memory until now.
> That said the test stream have 8 tile columns which is unusual but 
> admitted by AV1 specifications.

Gentle ping,
Regards,
Benjamin

>
> Benjamin
>
>>
>> Nicolas
>>
>>> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
>>> Fixes: 727a400686a2 ("media: verisilicon: Add Rockchip AV1 decoder")
>>> ---
>>> .../media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c | 3 ++-
>>>   1 file changed, 2 insertions(+), 1 deletion(-)
>>>
>>> diff --git 
>>> a/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c 
>>> b/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c
>>> index cc4483857489..65e8f2d07400 100644
>>> --- a/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c
>>> +++ b/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c
>>> @@ -257,7 +257,8 @@ static int 
>>> rockchip_vpu981_av1_dec_tiles_reallocate(struct hantro_ctx *ctx)
>>>       struct hantro_dev *vpu = ctx->dev;
>>>       struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec;
>>>       struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls;
>>> -    unsigned int num_tile_cols = 1 << 
>>> ctrls->tile_group_entry->tile_col;
>>> +    const struct v4l2_av1_tile_info *tile_info = 
>>> &ctrls->frame->tile_info;
>>> +    unsigned int num_tile_cols = tile_info->tile_cols;
>>>       unsigned int height = ALIGN(ctrls->frame->frame_height_minus_1 
>>> + 1, 64);
>>>       unsigned int height_in_sb = height / 64;
>>>       unsigned int stripe_num = ((height + 8) + 63) / 64;
>>

  reply	other threads:[~2024-05-06 14:38 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-03-28  9:34 [PATCH] media: verisilicon: AV1: Be more fexible on postproc capabilities Benjamin Gaignard
2024-03-28  9:34 ` [PATCH] media: verisilicon: Fix auxiliary buffers allocation size Benjamin Gaignard
2024-04-04 18:00   ` Nicolas Dufresne
2024-04-05  8:13     ` Benjamin Gaignard
2024-05-06 14:38       ` Benjamin Gaignard [this message]
2024-05-13 14:52   ` Nicolas Dufresne
2024-04-04 17:59 ` [PATCH] media: verisilicon: AV1: Be more fexible on postproc capabilities Nicolas Dufresne
2024-04-05  8:17   ` Benjamin Gaignard
2024-05-06 14:38     ` Benjamin Gaignard
2024-05-13 14:55 ` Nicolas Dufresne

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