From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2BCBE347BC3 for ; Wed, 17 Dec 2025 08:12:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765959144; cv=none; b=nG6V8TQ/fy+vOtEL/Qh2iwq2+PqAaIVaoxY7RnlpQnZY1rgaquJMnpQJ5k4+LTC3QBgPbTYqd8rnfjevexw2wymL4wfmrboy1A/rf9dehb7yd9STzeJkdIhdp3zBd6MWRCQw0sbWNjKFI5IBBot6EdzVY40SynGEUfkKlNc5mmU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765959144; c=relaxed/simple; bh=iBA3WRyTH45vNuDwOPt/1aUDZ+zVt92hD1g9XaW5ia4=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=JsDXzUfIUoSia/gmVWn0hnkuYBYyl62EhwagHtur5GMZ4K5ov7szgycdZkihEgYpUFh/WgUkIEJLupATMUdrRakz6PsHg+DBh68JrIfbiiY6UFAfYAdcEDEEixadit+RRsCpBy28nFazgZSGKEMUXCiqIrsQo+PnspxaYbWgAJU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5D0DAFEC; Wed, 17 Dec 2025 00:12:13 -0800 (PST) Received: from [10.164.18.63] (MacBook-Pro.blr.arm.com [10.164.18.63]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 91EB93F73F; Wed, 17 Dec 2025 00:12:17 -0800 (PST) Message-ID: <3de2b568-66f8-432f-a501-b19ca6c3a805@arm.com> Date: Wed, 17 Dec 2025 13:42:14 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 08/13] arm64: mm: Simplify __flush_tlb_range_limit_excess() To: Ryan Roberts , Will Deacon , Ard Biesheuvel , Catalin Marinas , Mark Rutland , Linus Torvalds , Oliver Upton , Marc Zyngier , Linu Cherian Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20251216144601.2106412-1-ryan.roberts@arm.com> <20251216144601.2106412-9-ryan.roberts@arm.com> Content-Language: en-US From: Dev Jain In-Reply-To: <20251216144601.2106412-9-ryan.roberts@arm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 16/12/25 8:15 pm, Ryan Roberts wrote: > From: Will Deacon > > __flush_tlb_range_limit_excess() is unnecessarily complicated: > > - It takes a 'start', 'end' and 'pages' argument, whereas it only > needs 'pages' (which the caller has computed from the other two > arguments!). > > - It erroneously compares 'pages' with MAX_TLBI_RANGE_PAGES when > the system doesn't support range-based invalidation but the range to > be invalidated would result in fewer than MAX_DVM_OPS invalidations. > > Simplify the function so that it no longer takes the 'start' and 'end' > arguments and only considers the MAX_TLBI_RANGE_PAGES threshold on > systems that implement range-based invalidation. > > Signed-off-by: Will Deacon > Signed-off-by: Ryan Roberts > --- > arch/arm64/include/asm/tlbflush.h | 20 ++++++-------------- > 1 file changed, 6 insertions(+), 14 deletions(-) > > diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h > index 0e1902f66e01..3b72a71feac0 100644 > --- a/arch/arm64/include/asm/tlbflush.h > +++ b/arch/arm64/include/asm/tlbflush.h > @@ -527,21 +527,13 @@ static __always_inline void __flush_tlb_range_op(tlbi_op lop, tlbi_op rop, > #define __flush_s2_tlb_range_op(op, start, pages, stride, tlb_level) \ > __flush_tlb_range_op(op, r##op, start, pages, stride, 0, tlb_level, kvm_lpa2_is_enabled()) > > -static inline bool __flush_tlb_range_limit_excess(unsigned long start, > - unsigned long end, unsigned long pages, unsigned long stride) > +static inline bool __flush_tlb_range_limit_excess(unsigned long pages, > + unsigned long stride) > { > - /* > - * When the system does not support TLB range based flush > - * operation, (MAX_DVM_OPS - 1) pages can be handled. But > - * with TLB range based operation, MAX_TLBI_RANGE_PAGES > - * pages can be handled. > - */ > - if ((!system_supports_tlb_range() && > - (end - start) >= (MAX_DVM_OPS * stride)) || > - pages > MAX_TLBI_RANGE_PAGES) > + if (system_supports_tlb_range() && pages > MAX_TLBI_RANGE_PAGES) > return true; > > - return false; > + return pages >= (MAX_DVM_OPS * stride) >> PAGE_SHIFT; The function will return true if tlb range is supported, but ((MAX_DVM_OPS * stride) >> PAGE_SHIFT) < pages <= MAX_TLBI_RANGE_PAGES. So I think you need to do https://lore.kernel.org/all/1b15b4f0-5490-4dac-8344-e716dd189751@arm.com/ > } > > static inline void __flush_tlb_range_nosync(struct mm_struct *mm, > @@ -555,7 +547,7 @@ static inline void __flush_tlb_range_nosync(struct mm_struct *mm, > end = round_up(end, stride); > pages = (end - start) >> PAGE_SHIFT; > > - if (__flush_tlb_range_limit_excess(start, end, pages, stride)) { > + if (__flush_tlb_range_limit_excess(pages, stride)) { > flush_tlb_mm(mm); > return; > } > @@ -619,7 +611,7 @@ static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end > end = round_up(end, stride); > pages = (end - start) >> PAGE_SHIFT; > > - if (__flush_tlb_range_limit_excess(start, end, pages, stride)) { > + if (__flush_tlb_range_limit_excess(pages, stride)) { > flush_tlb_all(); > return; > }