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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id j70sm12876254pfd.208.2020.06.28.20.19.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Jun 2020 20:19:21 -0700 (PDT) From: Zong Li To: palmer@dabbelt.com, paul.walmsley@sifive.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Zong Li Subject: [RFC PATCH 1/6] dt-bindings: riscv: Add YAML documentation for PMU Date: Mon, 29 Jun 2020 11:19:10 +0800 Message-Id: <3de3a480517d167a3faae086aa8ab0c0c7141d99.1593397455.git.zong.li@sifive.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add device tree bindings for performance monitor unit. And it passes the dt_binding_check verification. Signed-off-by: Zong Li --- .../devicetree/bindings/riscv/pmu.yaml | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/riscv/pmu.yaml diff --git a/Documentation/devicetree/bindings/riscv/pmu.yaml b/Documentation/devicetree/bindings/riscv/pmu.yaml new file mode 100644 index 000000000000..f55ccbc6c685 --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/pmu.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/pmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V Performance Monitor Units + +maintainers: + - Zong Li + - Paul Walmsley + - Palmer Dabbelt + +properties: + compatible: + items: + - const: riscv,pmu + + riscv,width-base-cntr: + description: The width of cycle and instret CSRs. + $ref: /schemas/types.yaml#/definitions/uint32 + + riscv,width-event-cntr: + description: The width of hpmcounter CSRs. + $ref: /schemas/types.yaml#/definitions/uint32 + + riscv,n-event-cntr: + description: The number of hpmcounter CSRs. + $ref: /schemas/types.yaml#/definitions/uint32 + + riscv,hw-event-map: + description: The mapping of generic hardware events. Default is no mapping. + $ref: /schemas/types.yaml#/definitions/uint32-array + + riscv,hw-cache-event-map: + description: The mapping of generic hardware cache events. + Default is no mapping. + $ref: /schemas/types.yaml#/definitions/uint32-array + +required: + - compatible + - riscv,width-base-cntr + - riscv,width-event-cntr + - riscv,n-event-cntr + +additionalProperties: false + +examples: + - | + pmu { + compatible = "riscv,pmu"; + riscv,width-base-cntr = <64>; + riscv,width-event-cntr = <40>; + riscv,n-event-cntr = <2>; + riscv,hw-event-map = <0x0 0x0 0x1 0x1 0x3 0x0202 0x4 0x4000>; + riscv,hw-cache-event-map = <0x010201 0x0102 0x010204 0x0802>; + }; + +... -- 2.27.0