From: Matthias Brugger <matthias.bgg@gmail.com>
To: Yongqiang Niu <yongqiang.niu@mediatek.com>,
CK Hu <ck.hu@mediatek.com>,
Chun-Kuang Hu <chunkuang.hu@kernel.org>
Cc: Jassi Brar <jassisinghbrar@gmail.com>,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org,
Project_Global_Chrome_Upstream_Group@mediatek.com,
Hsin-Yi Wang <hsinyi@chromium.org>
Subject: Re: [PATCH v7, 2/3] mailbox: mtk-cmdq: add gce ddr enable support flow
Date: Fri, 30 Sep 2022 15:18:12 +0200 [thread overview]
Message-ID: <3de55ec9-568a-6240-c13a-f35adff228d3@gmail.com> (raw)
In-Reply-To: <20220930095915.13684-3-yongqiang.niu@mediatek.com>
On 30/09/2022 11:59, Yongqiang Niu wrote:
> add gce ddr enable control flow when gce suspend/resume
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> drivers/mailbox/mtk-cmdq-mailbox.c | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
> index 04eb44d89119..84a60750d0c4 100644
> --- a/drivers/mailbox/mtk-cmdq-mailbox.c
> +++ b/drivers/mailbox/mtk-cmdq-mailbox.c
> @@ -94,6 +94,21 @@ struct gce_plat {
> u32 gce_num;
> };
>
> +static void cmdq_sw_ddr_enable(struct cmdq *cmdq, bool enable)
> +{
> + if (!cmdq->sw_ddr_en)
> + return;
> +
> + WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks));
> +
> + if (enable)
> + writel(GCE_DDR_EN | GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE);
> + else
> + writel(GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE);
> +
> + clk_bulk_disable(cmdq->gce_num, cmdq->clocks);
> +}
> +
> u8 cmdq_get_shift_pa(struct mbox_chan *chan)
> {
> struct cmdq *cmdq = container_of(chan->mbox, struct cmdq, mbox);
> @@ -319,6 +334,8 @@ static int cmdq_suspend(struct device *dev)
> if (task_running)
> dev_warn(dev, "exist running task(s) in suspend\n");
>
> + cmdq_sw_ddr_enable(cmdq, false);
I'd say
if (!cmdq->sw_ddr_en)
should be checked before calling cmdq_sw_ddr_enable().
Regards,
Matthias
> +
> clk_bulk_unprepare(cmdq->gce_num, cmdq->clocks);
>
> return 0;
> @@ -330,6 +347,9 @@ static int cmdq_resume(struct device *dev)
>
> WARN_ON(clk_bulk_prepare(cmdq->gce_num, cmdq->clocks));
> cmdq->suspended = false;
> +
> + cmdq_sw_ddr_enable(cmdq, true);
> +
> return 0;
> }
>
> @@ -337,6 +357,8 @@ static int cmdq_remove(struct platform_device *pdev)
> {
> struct cmdq *cmdq = platform_get_drvdata(pdev);
>
> + cmdq_sw_ddr_enable(cmdq, false);
> +
> clk_bulk_unprepare(cmdq->gce_num, cmdq->clocks);
> return 0;
> }
next prev parent reply other threads:[~2022-09-30 13:18 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-30 9:59 [PATCH v7, 0/3] mailbox: mtk-cmdq: add MT8186 support Yongqiang Niu
2022-09-30 9:59 ` [PATCH v7, 1/3] mailbox: mtk-cmdq: add gce software ddr enable private data Yongqiang Niu
2022-09-30 13:20 ` Matthias Brugger
2022-09-30 9:59 ` [PATCH v7, 2/3] mailbox: mtk-cmdq: add gce ddr enable support flow Yongqiang Niu
2022-09-30 13:18 ` Matthias Brugger [this message]
2022-09-30 9:59 ` [PATCH v7, 3/3] mailbox: mtk-cmdq: add MT8186 support Yongqiang Niu
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