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Mon, 06 Jul 2026 12:56:14 -0700 (PDT) X-Received: by 2002:a05:6a20:5499:b0:3bf:9e25:1a18 with SMTP id adf61e73a8af0-3c08ef55ba0mr2517836637.52.1783367774370; Mon, 06 Jul 2026 12:56:14 -0700 (PDT) Received: from [192.168.1.9] ([106.222.230.254]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-30f0b816a42sm90197173eec.9.2026.07.06.12.56.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 06 Jul 2026 12:56:13 -0700 (PDT) Message-ID: <3dea2be9-7c72-4c5a-865c-139837d294c1@oss.qualcomm.com> Date: Tue, 7 Jul 2026 01:26:02 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/8] drm/msm/a6xx: Add Adreno 722 support To: Konrad Dybcio Cc: Puranam V G Tejaswi , Abel Vesa , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Will Deacon , Robin Murphy , "Joerg Roedel (AMD)" References: <20260705-eliza-gpu-v1-0-c9f1354dbd29@oss.qualcomm.com> <20260705-eliza-gpu-v1-3-c9f1354dbd29@oss.qualcomm.com> From: Akhil P Oommen Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: a8AEeabqQPpn7cR_zcoGWyHtwjYUMTe3 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzA2MDIwMSBTYWx0ZWRfX2TF0/9LJ0Jzv Jqk/tJRbrdezJQWtEJFivQNE79rIgMaHk++1IHzldszNmOQH3DUBUzn0W8/ETKRSZiz1kdsU7md Lpi9afShEmHp1Zw9L23/Q8gmJGNlKHrQWbuTBWxCCvUkBC4x2yW8OExybprwZo/lbTav+mX8uSu A7GoyxRD9S/GaY3rSC6Ad6EmaxRNWHv+XFK0OaMUatF+LLpAZpEh6eX2DQgPXyu+S4gJqSAM2+B SSY84fqz8poN1sLPSxXzWkUuJBTjwV/+i1JOouSlSEw5UoM9BuvAviNrnIT4ZiB5ofcqYVCyIRq VM0j7El3d41y0aVnoRTOIPBJJWc2GDpw2KO9h5LiG7JrqAE2nxG7FDSzV/mzWYZbnUyHFXuS1y5 Aexzp9SNcytA1DW0OKcCKChCMrfOdEDj9uvdtP8R+TCjxa5nkBUixwszcgDp4DXzCYcmtZsQsFq opvDPwU36+4QryjUoGg== X-Proofpoint-ORIG-GUID: a8AEeabqQPpn7cR_zcoGWyHtwjYUMTe3 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzA2MDIwMSBTYWx0ZWRfX2I/XzBJZBo6a nxq4LW20IkX/VwbeCFXA2gpskIzGuMUu4A821H2+IjCu5vk3216MIaCDswMdSqO0aaXOXcqBs4X TFJIMhJ/Jw5SSkgxHXuWLJdZDiHRnBU= X-Authority-Analysis: v=2.4 cv=c6Sbhx9l c=1 sm=1 tr=0 ts=6a4c085f cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=fsdq8dFr2Uux402FS9br8A==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=Gg-SMJLLMV3ST4U2SEgA:9 a=QEXdDO2ut3YA:10 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-06_02,2026-07-06_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 clxscore=1015 adultscore=0 priorityscore=1501 lowpriorityscore=0 spamscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607060201 On 7/6/2026 2:29 PM, Konrad Dybcio wrote: > On 7/5/26 10:14 AM, Akhil P Oommen wrote: >> From: Puranam V G Tejaswi >> >> Add support for Adreno A722, a member of the GEN1 A7xx family. It is >> derived from A730 and shares the same IP-level configurations: HWCG >> registers, protected registers, GBIF CX registers and gmu_cgc_mode. >> Major differences include lower cache/core counts, 1MB GMEM, no >> Concurrent Binning & LPAC support. Some of the peripheral blocks like >> RSCC are from A740 that resulted in updates to RSC layout. >> >> Add a new entry to the catalog to describe the usual configuration and >> few additional fixup mainly due to missing CB/LPAC features and updated >> RSC layout. >> >> Signed-off-by: Puranam V G Tejaswi >> Signed-off-by: Akhil P Oommen >> --- > > [...] > >> --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >> @@ -710,7 +710,8 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) >> gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 2, 0); >> gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 2, 0); >> gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 4, >> - adreno_is_a740_family(adreno_gpu) ? 0x80000021 : 0x80000000); >> + (adreno_is_a740_family(adreno_gpu) || >> + adreno_is_a722(adreno_gpu)) ? 0x80000021 : 0x80000000); > > This is a discrepancy vs kgsl (did you look at gen7_14 instead of > gen7_17? did you test this on device?) Both 7_17 and 7_14 are same GPU IP. Yes, this was tested on Eliza MTP. > > [...] > >> /* The second spin of A7xx GPUs messed with some register offsets.. */ >> - if (adreno_is_a740_family(adreno_gpu)) >> + if (adreno_is_a740_family(adreno_gpu) || adreno_is_a722(adreno_gpu)) >> seqmem0_drv0_reg = REG_A7XX_RSCC_SEQ_MEM_0_DRV0_A740; > > Likewise > > [...] > >> /* The second spin of A7xx GPUs messed with some register offsets.. */ >> - if (adreno_is_a740_family(adreno_gpu) || adreno_is_a8xx(adreno_gpu)) >> + if (adreno_is_a740_family(adreno_gpu) || adreno_is_a722(adreno_gpu) || >> + adreno_is_a8xx(adreno_gpu)) >> seqmem_off = 4; > > Likewise > >> >> /* Make sure there are no outstanding RPMh votes */ >> @@ -1100,7 +1104,8 @@ static void a6xx_gmu_rpmh_off(struct a6xx_gmu *gmu) >> gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS3_DRV0_STATUS + seqmem_off, >> val, (val & 1), 100, 1000); >> >> - if (!adreno_is_a740_family(adreno_gpu) && !adreno_is_a8xx(adreno_gpu)) >> + if (!adreno_is_a740_family(adreno_gpu) && !adreno_is_a722(adreno_gpu) && >> + !adreno_is_a8xx(adreno_gpu)) >> return; > > Likewise > > You also need to if-out concurrent binning for this SKU You mean the PM4 pkts? If yes, fw will skip them as NOP. -Akhil. > > Konrad