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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ae6e7ee46cdsm819147066b.60.2025.07.14.04.06.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 14 Jul 2025 04:06:20 -0700 (PDT) Message-ID: <3e0299ad-766a-4876-912e-438fe2cc856d@oss.qualcomm.com> Date: Mon, 14 Jul 2025 13:06:17 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 14/15] arm64: dts: qcom: Add initial Milos dtsi To: Luca Weiss , Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Viresh Kumar , Manivannan Sadhasivam , Herbert Xu , "David S. Miller" , Vinod Koul , Bjorn Andersson , Konrad Dybcio , Robert Marko , Das Srinagesh , Thomas Gleixner , Jassi Brar , Amit Kucheria , Thara Gopinath , Daniel Lezcano , Zhang Rui , Lukasz Luba , Ulf Hansson Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, dmaengine@vger.kernel.org, linux-mmc@vger.kernel.org References: <20250713-sm7635-fp6-initial-v2-0-e8f9a789505b@fairphone.com> <20250713-sm7635-fp6-initial-v2-14-e8f9a789505b@fairphone.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20250713-sm7635-fp6-initial-v2-14-e8f9a789505b@fairphone.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzE0MDA2MyBTYWx0ZWRfX1wkwpOCAAFCI IcFsyw7+oS2BG1FXay41uy9ziVmTDaCRWxz0247yfjxa4S+FxeDskSvC5m8quLtrlaTrm0lV2uG XsyJwDAmXaPpRJmV2r6zyWVhLY5BRe51IT7DnqaKT0GYQWtMLoq4Xix1efMPFldZQ4wDM0/H2a1 RDx1DEyGQBVbESpEary/9/uWGGI6UJGACPJODCw9hIY8YFQA/7rv0TOFUj9JZeTNWnZrXHAhhyA Edn9aawNn/b+G15ls3Sw/tyII+OHsBBIM8US8ZinTXBuHreqd1GC8I1skNKbzmvwaIEGZRFJ7tW 3SmuhgnRHWIipTT8V6KTYF6vYKJkSBsR9niNQcnSmoGuK1w+6XGR9PKDBhRNtv4rAZzZKJGxyHX D1TXVhLL3ENxta4v7uuJ73By05VgOS4MK/3iXsXPh5kK8UfQnLWatUbvuDP8EoJ60AN5Ow7A X-Proofpoint-ORIG-GUID: 1la3LgdYh3bpH9qE40Jm4OapbWDsyvzM X-Proofpoint-GUID: 1la3LgdYh3bpH9qE40Jm4OapbWDsyvzM X-Authority-Analysis: v=2.4 cv=f59IBPyM c=1 sm=1 tr=0 ts=6874e4af cx=c_pps a=WeENfcodrlLV9YRTxbY/uA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=6H0WHjuAAAAA:8 a=N13MPgUakCYYuvbLhsgA:9 a=QEXdDO2ut3YA:10 a=kacYvNCVWA4VmyqE58fU:22 a=Soq9LBFxuPC4vsCAQt-j:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-14_01,2025-07-14_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 malwarescore=0 spamscore=0 mlxscore=0 bulkscore=0 suspectscore=0 impostorscore=0 adultscore=0 priorityscore=1501 mlxlogscore=999 phishscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507140063 On 7/13/25 10:05 AM, Luca Weiss wrote: > Add a devicetree description for the Milos SoC, which is for example > Snapdragon 7s Gen 3 (SM7635). > > Signed-off-by: Luca Weiss > --- [...] > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&cpu0>; > + }; > + > + core1 { > + cpu = <&cpu1>; > + }; > + > + core2 { > + cpu = <&cpu2>; > + }; > + > + core3 { > + cpu = <&cpu3>; > + }; > + }; > + > + cluster1 { > + core0 { > + cpu = <&cpu4>; > + }; > + > + core1 { > + cpu = <&cpu5>; > + }; > + > + core2 { > + cpu = <&cpu6>; > + }; > + }; > + > + cluster2 { > + core0 { > + cpu = <&cpu7>; > + }; > + }; > + }; I'm getting mixed information about the core topology.. What does dmesg say wrt this line? CPU%u: Booted secondary processor 0x%010lx [0x%08x]\n > + pmu-a520 { > + compatible = "arm,cortex-a520-pmu"; > + interrupts = ; > + }; > + > + pmu-a720 { > + compatible = "arm,cortex-a720-pmu"; > + interrupts = ; > + }; See: 9ce52e908bd5 ("arm64: dts: qcom: sm8650: switch to interrupt-cells 4 to add PPI partitions") 2c06e0797c32 ("arm64: dts: qcom: sm8650: add PPI interrupt partitions for the ARM PMUs") [...] > + gcc: clock-controller@100000 { > + compatible = "qcom,milos-gcc"; > + reg = <0x0 0x00100000 0x0 0x1f4200>; > + > + clocks = <&rpmhcc RPMH_CXO_CLK>, > + <&sleep_clk>, > + <0>, /* pcie_0_pipe_clk */ > + <0>, /* pcie_1_pipe_clk */ > + <0>, /* ufs_phy_rx_symbol_0_clk */ > + <0>, /* ufs_phy_rx_symbol_1_clk */ > + <0>, /* ufs_phy_tx_symbol_0_clk */ > + <0>; /* usb3_phy_wrapper_gcc_usb30_pipe_clk */ > + protected-clocks = , , > + , , > + , , > + , , > + , , > + , ; Does access control disallow accessing these on your prod-fused device? [...] > + usb_1: usb@a600000 { > + compatible = "qcom,milos-dwc3", "qcom,snps-dwc3"; > + reg = <0x0 0x0a600000 0x0 0x10000>; size = 0xfc_000 [...] > + > + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, > + <&gcc GCC_USB30_PRIM_MASTER_CLK>, > + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, > + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, > + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, > + <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "cfg_noc", > + "core", > + "iface", > + "sleep", > + "mock_utmi", > + "xo"; > + > + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, > + <&gcc GCC_USB30_PRIM_MASTER_CLK>; > + assigned-clock-rates = <19200000>, <133333333>; Set the latter to 200000000 - your device doesn't have USB3, but the next person may lose their hair about tracking down why it doesn't work on theirs [...] > + pdc: interrupt-controller@b220000 { > + compatible = "qcom,milos-pdc", "qcom,pdc"; > + reg = <0x0 0x0b220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>; 1 per line, please > + interrupt-parent = <&intc>; > + > + qcom,pdc-ranges = <0 480 40>, <40 140 11>, <51 527 47>, > + <98 609 31>, <129 63 1>, <130 716 12>, > + <142 251 5>; > + > + #interrupt-cells = <2>; > + interrupt-controller; > + }; > + > + tsens0: thermal-sensor@c228000 { > + compatible = "qcom,milos-tsens", "qcom,tsens-v2"; > + reg = <0x0 0x0c228000 0x0 0x1ff>, /* TM */ > + <0x0 0x0c222000 0x0 0x1ff>; /* SROT */ drop the comments the sizes are 0x1000 for both regions for both controllers > + > + interrupts = , pdc 26 > + ; > + interrupt-names = "uplow", > + "critical"; > + > + #qcom,sensors = <15>; > + > + #thermal-sensor-cells = <1>; > + }; > + > + tsens1: thermal-sensor@c229000 { > + compatible = "qcom,milos-tsens", "qcom,tsens-v2"; > + reg = <0x0 0x0c229000 0x0 0x1ff>, /* TM */ > + <0x0 0x0c223000 0x0 0x1ff>; /* SROT */ > + > + interrupts = , pdc 27 > + ; > + interrupt-names = "uplow", > + "critical"; > + > + #qcom,sensors = <14>; > + > + #thermal-sensor-cells = <1>; > + }; > + > + aoss_qmp: power-management@c300000 { > + compatible = "qcom,milos-aoss-qmp", "qcom,aoss-qmp"; > + reg = <0x0 0x0c300000 0x0 0x400>; > + > + interrupt-parent = <&ipcc>; > + interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP > + IRQ_TYPE_EDGE_RISING>; > + > + mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; > + > + #clock-cells = <0>; > + }; > + > + sram@c3f0000 { > + compatible = "qcom,rpmh-stats"; > + reg = <0x0 0x0c3f0000 0x0 0x400>; > + }; > + > + spmi_bus: spmi@c400000 { > + compatible = "qcom,spmi-pmic-arb"; There's two bus instances on this platform, check out the x1e binding [...] > + intc: interrupt-controller@17100000 { > + compatible = "arm,gic-v3"; > + reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */ > + <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */ drop the comments please [...] > + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; > + clock-names = "xo", "alternate"; 1 a line, please [...] > + cpuss0-thermal { > + thermal-sensors = <&tsens0 1>; > + > + trips { > + cpuss0-hot { > + temperature = <110000>; > + hysteresis = <1000>; > + type = "hot"; > + }; > + > + cpuss0-critical { > + temperature = <115000>; > + hysteresis = <0>; > + type = "critical"; > + }; > + }; > + }; See: 06eadce93697 ("arm64: dts: qcom: x1e80100: Drop unused passive thermal trip points for CPU") (tldr drop non-critical trips for CPU) Konrad