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[51.91.159.9]) by smtp.gmail.com with ESMTPSA id v5-20020adfa1c5000000b0032d81837433sm7445222wrv.30.2023.11.09.05.44.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 09 Nov 2023 05:44:47 -0800 (PST) Message-ID: <3e0958a9-4d1e-4d1b-a914-5da154caa11f@linaro.org> Date: Thu, 9 Nov 2023 14:44:44 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 4/6] media: qcom: camss: Add sc8280xp resource details Content-Language: en-US To: Bryan O'Donoghue , hverkuil-cisco@xs4all.nl, laurent.pinchart@ideasonboard.com, Andy Gross , Bjorn Andersson , Robert Foss , Todor Tomov , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , vincent.knecht@mailoo.org, matti.lehtimaki@gmail.com, quic_grosikop@quicinc.com Cc: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20231109-b4-camss-sc8280xp-v4-0-58a58bc200f9@linaro.org> <20231109-b4-camss-sc8280xp-v4-4-58a58bc200f9@linaro.org> From: Konrad Dybcio In-Reply-To: <20231109-b4-camss-sc8280xp-v4-4-58a58bc200f9@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 11/9/23 12:30, Bryan O'Donoghue wrote: > This commit describes the hardware layout for the sc8280xp for the > following hardware blocks: > > - 4 x VFE, 4 RDI per VFE > - 4 x VFE Lite, 4 RDI per VFE > - 4 x CSID > - 4 x CSID Lite > - 4 x CSI PHY > > Signed-off-by: Bryan O'Donoghue > --- [...] > +static const struct camss_subdev_resources csid_res_sc8280xp[] = { > + /* CSID0 */ > + { > + .regulators = { "vdda-phy", "vdda-pll" }, > + .clock = { "vfe0_csid", "vfe0_cphy_rx", "vfe0", "vfe0_axi" }, > + .clock_rate = { { 400000000, 400000000, 480000000, 600000000, 600000000, 600000000 }, (why is it 400, 400, 480, 600, 600, 600 and not 400, 480, 600?) > + { 0 }, > + { 0 }, > + { 0 } }, There's a funny bug.. camss-csiphy.c and camss-vfe.c (sounds like room for commonization): while (res->clock_rate[i][clock->nfreqs]) clock->nfreqs++; this works fine in this case, because the last frequency is followed by a zero, so overflowing the 2nd dimension of the array into the last+1 member (meaning the first member of the following entry in the 1st dimension) stops this loop however [...] > +static const struct camss_subdev_resources vfe_res_sc8280xp[] = { > + /* IFE0 */ > + { > + .regulators = {}, > + .clock = { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb", "camnoc_axi", "vfe0", "vfe0_axi" }, > + .clock_rate = { { 0 }, > + { 0 }, > + { 19200000, 80000000, 80000000, 80000000, 80000000}, > + { 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 }, > + { 400000000, 558000000, 637000000, 760000000 }, > + { 0 }, }, Not the case here! I'd suggest moving this to something like: struct res_clk_data { const char * const names; const u64 * const rates; (or unsigned long / unsigned long long / uint? there was some capping for arm32) const u8 num_clks; } OR even better separate out clocks that just need to be on/off ("intf/interface clocks" sounds like a good name for these) from ones that require scaling, use clk_bulk apis for the former and OPP for the latter to make sure the correct performance state is requested on the RPMhPDs Konrad